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Reland "[AArch64] AArch64TargetLowering::computeKnownBitsForTargetNode - add support for AArch64ISD::MOV/MVN constants" (#155696)
Reland #154039 Per suggestion by @davemgreen, add mask on the shift amount to prevent shifting more than the bitwidth. This change is confirmed to fix the tests failures on x86 sanitizer bots and aarch64 sanitizer bots failures. Fixes: #153159
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‎llvm/lib/Target/AArch64/AArch64ISelLowering.cpp

Lines changed: 36 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -2664,6 +2664,32 @@ void AArch64TargetLowering::computeKnownBitsForTargetNode(
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<< Op->getConstantOperandVal(1)));
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break;
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}
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case AArch64ISD::MOVImsl: {
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unsigned ShiftAmt = AArch64_AM::getShiftValue(Op->getConstantOperandVal(1));
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Known = KnownBits::makeConstant(APInt(
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Known.getBitWidth(), ~(~Op->getConstantOperandVal(0) << ShiftAmt)));
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break;
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}
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case AArch64ISD::MOVIedit: {
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Known = KnownBits::makeConstant(APInt(
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Known.getBitWidth(),
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AArch64_AM::decodeAdvSIMDModImmType10(Op->getConstantOperandVal(0))));
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break;
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}
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case AArch64ISD::MVNIshift: {
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Known = KnownBits::makeConstant(
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APInt(Known.getBitWidth(),
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~(Op->getConstantOperandVal(0) << Op->getConstantOperandVal(1)),
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/*isSigned*/ false, /*implicitTrunc*/ true));
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break;
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}
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case AArch64ISD::MVNImsl: {
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unsigned ShiftAmt = AArch64_AM::getShiftValue(Op->getConstantOperandVal(1));
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Known = KnownBits::makeConstant(
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APInt(Known.getBitWidth(), (~Op->getConstantOperandVal(0) << ShiftAmt),
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/*isSigned*/ false, /*implicitTrunc*/ true));
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break;
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}
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case AArch64ISD::LOADgot:
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case AArch64ISD::ADDlow: {
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if (!Subtarget->isTargetILP32())
@@ -30805,6 +30831,16 @@ bool AArch64TargetLowering::isTargetCanonicalConstantNode(SDValue Op) const {
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return Op.getOpcode() == AArch64ISD::DUP ||
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Op.getOpcode() == AArch64ISD::MOVI ||
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Op.getOpcode() == AArch64ISD::MOVIshift ||
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Op.getOpcode() == AArch64ISD::MOVImsl ||
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Op.getOpcode() == AArch64ISD::MOVIedit ||
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Op.getOpcode() == AArch64ISD::MVNIshift ||
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Op.getOpcode() == AArch64ISD::MVNImsl ||
30838+
// Ignoring fneg(movi(0)), because if it is folded to FPConstant(-0.0),
30839+
// ISel will select fmov(mov i64 0x8000000000000000), resulting in a
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// fmov from fpr to gpr, which is more expensive than fneg(movi(0))
30841+
(Op.getOpcode() == ISD::FNEG &&
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Op.getOperand(0).getOpcode() == AArch64ISD::MOVIedit &&
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Op.getOperand(0).getConstantOperandVal(0) == 0) ||
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(Op.getOpcode() == ISD::EXTRACT_SUBVECTOR &&
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Op.getOperand(0).getOpcode() == AArch64ISD::DUP) ||
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TargetLowering::isTargetCanonicalConstantNode(Op);

‎llvm/unittests/Target/AArch64/AArch64SelectionDAGTest.cpp

Lines changed: 114 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -318,6 +318,120 @@ TEST_F(AArch64SelectionDAGTest, ComputeKnownBits_UADDO_CARRY) {
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EXPECT_EQ(Known.One, APInt(8, 0x86));
319319
}
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// Piggy-backing on the AArch64 tests to verify SelectionDAG::computeKnownBits.
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TEST_F(AArch64SelectionDAGTest, ComputeKnownBits_MOVI) {
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SDLoc Loc;
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auto IntSca32VT = MVT::i32;
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auto Int8Vec8VT = MVT::v8i8;
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auto Int16Vec8VT = MVT::v16i8;
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auto Int4Vec16VT = MVT::v4i16;
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auto Int8Vec16VT = MVT::v8i16;
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auto Int2Vec32VT = MVT::v2i32;
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auto Int4Vec32VT = MVT::v4i32;
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auto IntVec64VT = MVT::v1i64;
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auto Int2Vec64VT = MVT::v2i64;
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auto N165 = DAG->getConstant(0x000000A5, Loc, IntSca32VT);
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KnownBits Known;
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auto OpMOVIedit64 = DAG->getNode(AArch64ISD::MOVIedit, Loc, IntVec64VT, N165);
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Known = DAG->computeKnownBits(OpMOVIedit64);
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EXPECT_EQ(Known.Zero, APInt(64, 0x00FF00FFFF00FF00));
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EXPECT_EQ(Known.One, APInt(64, 0xFF00FF0000FF00FF));
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auto OpMOVIedit128 =
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DAG->getNode(AArch64ISD::MOVIedit, Loc, Int2Vec64VT, N165);
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Known = DAG->computeKnownBits(OpMOVIedit128);
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EXPECT_EQ(Known.Zero, APInt(64, 0x00FF00FFFF00FF00));
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EXPECT_EQ(Known.One, APInt(64, 0xFF00FF0000FF00FF));
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auto N264 = DAG->getConstant(264, Loc, IntSca32VT);
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auto OpMOVImsl64 =
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DAG->getNode(AArch64ISD::MOVImsl, Loc, Int2Vec32VT, N165, N264);
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Known = DAG->computeKnownBits(OpMOVImsl64);
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EXPECT_EQ(Known.Zero, APInt(32, 0xFFFF5A00));
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EXPECT_EQ(Known.One, APInt(32, 0x0000A5FF));
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auto N272 = DAG->getConstant(272, Loc, IntSca32VT);
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auto OpMOVImsl128 =
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DAG->getNode(AArch64ISD::MOVImsl, Loc, Int4Vec32VT, N165, N272);
357+
Known = DAG->computeKnownBits(OpMOVImsl128);
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EXPECT_EQ(Known.Zero, APInt(32, 0xFF5A0000));
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EXPECT_EQ(Known.One, APInt(32, 0x00A5FFFF));
360+
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auto OpMVNImsl64 =
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DAG->getNode(AArch64ISD::MVNImsl, Loc, Int2Vec32VT, N165, N272);
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Known = DAG->computeKnownBits(OpMVNImsl64);
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EXPECT_EQ(Known.Zero, APInt(32, 0x00A5FFFF));
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EXPECT_EQ(Known.One, APInt(32, 0xFF5A0000));
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auto OpMVNImsl128 =
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DAG->getNode(AArch64ISD::MVNImsl, Loc, Int4Vec32VT, N165, N264);
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Known = DAG->computeKnownBits(OpMVNImsl128);
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EXPECT_EQ(Known.Zero, APInt(32, 0x0000A5FF));
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EXPECT_EQ(Known.One, APInt(32, 0xFFFF5A00));
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auto N0 = DAG->getConstant(0, Loc, IntSca32VT);
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auto OpMOVIshift2Vec32 =
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DAG->getNode(AArch64ISD::MOVIshift, Loc, Int2Vec32VT, N165, N0);
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Known = DAG->computeKnownBits(OpMOVIshift2Vec32);
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EXPECT_EQ(Known.Zero, APInt(32, 0xFFFFFF5A));
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EXPECT_EQ(Known.One, APInt(32, 0x000000A5));
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auto N24 = DAG->getConstant(24, Loc, IntSca32VT);
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auto OpMOVIshift4Vec32 =
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DAG->getNode(AArch64ISD::MOVIshift, Loc, Int4Vec32VT, N165, N24);
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Known = DAG->computeKnownBits(OpMOVIshift4Vec32);
384+
EXPECT_EQ(Known.Zero, APInt(32, 0x5AFFFFFF));
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EXPECT_EQ(Known.One, APInt(32, 0xA5000000));
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auto OpMVNIshift2Vec32 =
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DAG->getNode(AArch64ISD::MVNIshift, Loc, Int2Vec32VT, N165, N24);
389+
Known = DAG->computeKnownBits(OpMVNIshift2Vec32);
390+
EXPECT_EQ(Known.Zero, APInt(32, 0xA5000000));
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EXPECT_EQ(Known.One, APInt(32, 0x5AFFFFFF));
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auto OpMVNIshift4Vec32 =
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DAG->getNode(AArch64ISD::MVNIshift, Loc, Int4Vec32VT, N165, N0);
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Known = DAG->computeKnownBits(OpMVNIshift4Vec32);
396+
EXPECT_EQ(Known.Zero, APInt(32, 0x000000A5));
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EXPECT_EQ(Known.One, APInt(32, 0xFFFFFF5A));
398+
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auto N8 = DAG->getConstant(8, Loc, IntSca32VT);
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auto OpMOVIshift4Vec16 =
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DAG->getNode(AArch64ISD::MOVIshift, Loc, Int4Vec16VT, N165, N0);
402+
Known = DAG->computeKnownBits(OpMOVIshift4Vec16);
403+
EXPECT_EQ(Known.Zero, APInt(16, 0xFF5A));
404+
EXPECT_EQ(Known.One, APInt(16, 0x00A5));
405+
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auto OpMOVIshift8Vec16 =
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DAG->getNode(AArch64ISD::MOVIshift, Loc, Int8Vec16VT, N165, N8);
408+
Known = DAG->computeKnownBits(OpMOVIshift8Vec16);
409+
EXPECT_EQ(Known.Zero, APInt(16, 0x5AFF));
410+
EXPECT_EQ(Known.One, APInt(16, 0xA500));
411+
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auto OpMVNIshift4Vec16 =
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DAG->getNode(AArch64ISD::MVNIshift, Loc, Int4Vec16VT, N165, N8);
414+
Known = DAG->computeKnownBits(OpMVNIshift4Vec16);
415+
EXPECT_EQ(Known.Zero, APInt(16, 0xA500));
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EXPECT_EQ(Known.One, APInt(16, 0x5AFF));
417+
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auto OpMVNIshift8Vec16 =
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DAG->getNode(AArch64ISD::MVNIshift, Loc, Int8Vec16VT, N165, N0);
420+
Known = DAG->computeKnownBits(OpMVNIshift8Vec16);
421+
EXPECT_EQ(Known.Zero, APInt(16, 0x00A5));
422+
EXPECT_EQ(Known.One, APInt(16, 0xFF5A));
423+
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auto OpMOVI8Vec8 = DAG->getNode(AArch64ISD::MOVI, Loc, Int8Vec8VT, N165);
425+
Known = DAG->computeKnownBits(OpMOVI8Vec8);
426+
EXPECT_EQ(Known.Zero, APInt(8, 0x5A));
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EXPECT_EQ(Known.One, APInt(8, 0xA5));
428+
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auto OpMOVI16Vec8 = DAG->getNode(AArch64ISD::MOVI, Loc, Int16Vec8VT, N165);
430+
Known = DAG->computeKnownBits(OpMOVI16Vec8);
431+
EXPECT_EQ(Known.Zero, APInt(8, 0x5A));
432+
EXPECT_EQ(Known.One, APInt(8, 0xA5));
433+
}
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321435
// Piggy-backing on the AArch64 tests to verify SelectionDAG::computeKnownBits.
322436
TEST_F(AArch64SelectionDAGTest, ComputeKnownBits_SUB) {
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SDLoc Loc;

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