@@ -10976,28 +10976,28 @@ SDValue DAGCombiner::visitSRL(SDNode *N) {
1097610976 // -> (logic_op (srl x, c1), (zext y))
1097710977 // c1 <= leadingzeros(zext(y))
1097810978 if (N1C && ISD::isBitwiseLogicOp(N0.getOpcode()) && N0.hasOneUse()) {
10979- SDValue lhs = N0.getOperand(0);
10980- SDValue rhs = N0.getOperand(1);
10981- SDValue shl ;
10982- SDValue other ;
10983- if (lhs .getOpcode() == ISD::SHL) {
10984- shl = lhs ;
10985- other = rhs ;
10986- } else if (rhs .getOpcode() == ISD::SHL) {
10987- shl = rhs ;
10988- other = lhs ;
10989- }
10990- if (shl && shl .getOperand(1) == N1 && shl .hasOneUse()) {
10991- SDValue zext = shl .getOperand(0);
10992- if (zext .getOpcode() == ISD::ZERO_EXTEND) {
10993- unsigned numLeadingZeros =
10994- zext .getValueType().getScalarSizeInBits() -
10995- zext .getOperand(0).getValueType().getScalarSizeInBits();
10996- if (N1C->getZExtValue() <= numLeadingZeros ) {
10979+ SDValue LHS = N0.getOperand(0);
10980+ SDValue RHS = N0.getOperand(1);
10981+ SDValue SHL ;
10982+ SDValue Other ;
10983+ if (LHS .getOpcode() == ISD::SHL) {
10984+ SHL = LHS ;
10985+ Other = RHS ;
10986+ } else if (RHS .getOpcode() == ISD::SHL) {
10987+ SHL = RHS ;
10988+ Other = LHS ;
10989+ }
10990+ if (SHL && SHL .getOperand(1) == N1 && SHL .hasOneUse()) {
10991+ SDValue ZExt = SHL .getOperand(0);
10992+ if (ZExt .getOpcode() == ISD::ZERO_EXTEND) {
10993+ unsigned NumLeadingZeros =
10994+ ZExt .getValueType().getScalarSizeInBits() -
10995+ ZExt .getOperand(0).getValueType().getScalarSizeInBits();
10996+ if (N1C->getZExtValue() <= NumLeadingZeros ) {
1099710997 return DAG.getNode(
1099810998 N0.getOpcode(), SDLoc(N0), VT,
10999- DAG.getNode(ISD::SRL, SDLoc(N0), VT, other , N1),
11000- zext );
10999+ DAG.getNode(ISD::SRL, SDLoc(N0), VT, Other , N1),
11000+ ZExt );
1100111001 }
1100211002 }
1100311003 }
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