Skip to content

Commit 9b88270

Browse files
jwanggit86jwanggit86
committed
For gfx11.
1 parent 56f7f6b commit 9b88270

File tree

2 files changed

+30
-6
lines changed

2 files changed

+30
-6
lines changed

‎llvm/lib/Target/AMDGPU/MIMGInstructions.td‎

Lines changed: 6 additions & 6 deletions
Original file line numberDiff line numberDiff line change
@@ -474,7 +474,7 @@ class MIMG_NoSampler_gfx11<mimgopc op, string opcode,
474474
RegisterClass DataRC, RegisterClass AddrRC,
475475
string dns="">
476476
: MIMG_gfx11<op.GFX11, (outs DataRC:$vdata), dns> {
477-
let InOperandList = !con((ins AddrRC:$vaddr0, SReg_256_XNULL:$srsrc, DMask:$dmask,
477+
let InOperandList = !con((ins AddrRC:$vaddr0, SReg_RSRC:$srsrc, DMask:$dmask,
478478
Dim:$dim, UNorm:$unorm, CPol:$cpol,
479479
R128A16:$r128, A16:$a16, TFE:$tfe, LWE:$lwe),
480480
!if(BaseOpcode.HasD16, (ins D16:$d16), (ins)));
@@ -487,7 +487,7 @@ class MIMG_NoSampler_nsa_gfx11<mimgopc op, string opcode,
487487
string dns="">
488488
: MIMG_nsa_gfx11<op.GFX11, (outs DataRC:$vdata), num_addrs, dns> {
489489
let InOperandList = !con(AddrIns,
490-
(ins SReg_256_XNULL:$srsrc, DMask:$dmask,
490+
(ins SReg_RSRC:$srsrc, DMask:$dmask,
491491
Dim:$dim, UNorm:$unorm, CPol:$cpol,
492492
R128A16:$r128, A16:$a16, TFE:$tfe, LWE:$lwe),
493493
!if(BaseOpcode.HasD16, (ins D16:$d16), (ins)));
@@ -733,7 +733,7 @@ class MIMG_Store_gfx11<mimgopc op, string opcode,
733733
RegisterClass DataRC, RegisterClass AddrRC,
734734
string dns="">
735735
: MIMG_gfx11<op.GFX11, (outs), dns> {
736-
let InOperandList = !con((ins DataRC:$vdata, AddrRC:$vaddr0, SReg_256_XNULL:$srsrc,
736+
let InOperandList = !con((ins DataRC:$vdata, AddrRC:$vaddr0, SReg_RSRC:$srsrc,
737737
DMask:$dmask, Dim:$dim, UNorm:$unorm, CPol:$cpol,
738738
R128A16:$r128, A16:$a16, TFE:$tfe, LWE:$lwe),
739739
!if(BaseOpcode.HasD16, (ins D16:$d16), (ins)));
@@ -747,7 +747,7 @@ class MIMG_Store_nsa_gfx11<mimgopc op, string opcode,
747747
: MIMG_nsa_gfx11<op.GFX11, (outs), num_addrs, dns> {
748748
let InOperandList = !con((ins DataRC:$vdata),
749749
AddrIns,
750-
(ins SReg_256_XNULL:$srsrc, DMask:$dmask,
750+
(ins SReg_RSRC:$srsrc, DMask:$dmask,
751751
Dim:$dim, UNorm:$unorm, CPol:$cpol,
752752
R128A16:$r128, A16:$a16, TFE:$tfe, LWE:$lwe),
753753
!if(BaseOpcode.HasD16, (ins D16:$d16), (ins)));
@@ -951,7 +951,7 @@ class MIMG_Atomic_gfx11<mimgopc op, string opcode,
951951
!if(enableDisasm, "GFX11", "")> {
952952
let Constraints = "$vdst = $vdata";
953953

954-
let InOperandList = (ins DataRC:$vdata, AddrRC:$vaddr0, SReg_256_XNULL:$srsrc,
954+
let InOperandList = (ins DataRC:$vdata, AddrRC:$vaddr0, SReg_RSRC:$srsrc,
955955
DMask:$dmask, Dim:$dim, UNorm:$unorm, CPol:$cpol,
956956
R128A16:$r128, A16:$a16, TFE:$tfe, LWE:$lwe);
957957
let AsmString = opcode#" $vdst, $vaddr0, $srsrc$dmask$dim$unorm$cpol$r128$a16$tfe$lwe";
@@ -966,7 +966,7 @@ class MIMG_Atomic_nsa_gfx11<mimgopc op, string opcode,
966966

967967
let InOperandList = !con((ins DataRC:$vdata),
968968
AddrIns,
969-
(ins SReg_256_XNULL:$srsrc, DMask:$dmask,
969+
(ins SReg_RSRC:$srsrc, DMask:$dmask,
970970
Dim:$dim, UNorm:$unorm, CPol:$cpol,
971971
R128A16:$r128, A16:$a16, TFE:$tfe, LWE:$lwe));
972972
let AsmString = opcode#" $vdata, "#AddrAsm#", $srsrc$dmask$dim$unorm$cpol$r128$a16$tfe$lwe";

‎llvm/test/MC/AMDGPU/gfx11_asm_mimg.s‎

Lines changed: 24 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -3,6 +3,9 @@
33
image_atomic_add v[1:2], v2, s[12:19] dmask:0x3 dim:SQ_RSRC_IMG_1D unorm
44
// GFX11: [0x80,0x03,0x30,0xf0,0x02,0x01,0x03,0x00]
55

6+
image_atomic_add v[1:2], v2, s[12:15] dmask:0x3 dim:SQ_RSRC_IMG_1D unorm r128
7+
// GFX11: [0x80,0x83,0x30,0xf0,0x02,0x01,0x03,0x00]
8+
69
image_atomic_add v[1:2], v255, s[12:19] dmask:0x3 dim:SQ_RSRC_IMG_1D unorm
710
// GFX11: [0x80,0x03,0x30,0xf0,0xff,0x01,0x03,0x00]
811

@@ -1275,6 +1278,9 @@ image_bvh_intersect_ray v[252:255], v[248:255], ttmp[12:15] a16
12751278
image_gather4 v[5:8], v[1:2], s[8:15], s[12:15] dmask:0x4 dim:SQ_RSRC_IMG_2D
12761279
// GFX11: [0x04,0x04,0xbc,0xf0,0x01,0x05,0x02,0x0c]
12771280

1281+
image_gather4 v[5:8], v[1:2], s[8:11], s[12:15] dmask:0x4 dim:SQ_RSRC_IMG_2D r128
1282+
// GFX11: [0x04,0x84,0xbc,0xf0,0x01,0x05,0x02,0x0c]
1283+
12781284
image_gather4 v[5:8], v[254:255], s[8:15], s[12:15] dmask:0x4 dim:SQ_RSRC_IMG_2D
12791285
// GFX11: [0x04,0x04,0xbc,0xf0,0xfe,0x05,0x02,0x0c]
12801286

@@ -1815,6 +1821,9 @@ image_gather4h v[254:255], v[254:255], ttmp[8:15], ttmp[12:15] dmask:0x4 dim:SQ_
18151821
image_get_lod v[5:6], v1, s[8:15], s[12:15] dmask:0x3 dim:SQ_RSRC_IMG_1D
18161822
// GFX11: [0x00,0x03,0xe0,0xf0,0x01,0x05,0x02,0x0c]
18171823

1824+
image_get_lod v[5:6], v1, s[8:11], s[12:15] dmask:0x3 dim:SQ_RSRC_IMG_1D r128
1825+
// GFX11: [0x00,0x83,0xe0,0xf0,0x01,0x05,0x02,0x0c]
1826+
18181827
image_get_lod v[5:6], v255, s[8:15], s[12:15] dmask:0x3 dim:SQ_RSRC_IMG_1D
18191828
// GFX11: [0x00,0x03,0xe0,0xf0,0xff,0x05,0x02,0x0c]
18201829

@@ -1887,6 +1896,9 @@ image_get_lod v[254:255], v[254:255], ttmp[8:15], ttmp[12:15] dmask:0x4 dim:SQ_R
18871896
image_get_resinfo v[5:6], v1, s[8:15] dmask:0x3 dim:SQ_RSRC_IMG_1D
18881897
// GFX11: [0x00,0x03,0x5c,0xf0,0x01,0x05,0x02,0x00]
18891898

1899+
image_get_resinfo v[5:6], v1, s[8:11] dmask:0x3 dim:SQ_RSRC_IMG_1D r128
1900+
// GFX11: [0x00,0x83,0x5c,0xf0,0x01,0x05,0x02,0x00]
1901+
18901902
image_get_resinfo v[5:6], v255, s[8:15] dmask:0x3 dim:SQ_RSRC_IMG_1D
18911903
// GFX11: [0x00,0x03,0x5c,0xf0,0xff,0x05,0x02,0x00]
18921904

@@ -1959,6 +1971,9 @@ image_get_resinfo v[254:255], v255, ttmp[8:15] dmask:0x4 dim:SQ_RSRC_IMG_2D_ARRA
19591971
image_load v[5:6], v1, s[8:15] dmask:0x3 dim:SQ_RSRC_IMG_1D
19601972
// GFX11: [0x00,0x03,0x00,0xf0,0x01,0x05,0x02,0x00]
19611973

1974+
image_load v[5:6], v1, s[8:11] dmask:0x3 dim:SQ_RSRC_IMG_1D r128
1975+
// GFX11: [0x00,0x83,0x00,0xf0,0x01,0x05,0x02,0x00]
1976+
19621977
image_load v[5:6], v255, s[8:15] dmask:0x3 dim:SQ_RSRC_IMG_1D
19631978
// GFX11: [0x00,0x03,0x00,0xf0,0xff,0x05,0x02,0x00]
19641979

@@ -2463,6 +2478,9 @@ image_load_pck_sgn v[254:255], v[254:255], ttmp[8:15] dmask:0x4 dim:SQ_RSRC_IMG_
24632478
image_msaa_load v[5:8], v[1:4], s[8:15] dmask:0x4 dim:SQ_RSRC_IMG_2D_MSAA_ARRAY
24642479
// GFX11: [0x1c,0x04,0x60,0xf0,0x01,0x05,0x02,0x00]
24652480

2481+
image_msaa_load v[5:8], v[1:4], s[8:11] dmask:0x4 dim:SQ_RSRC_IMG_2D_MSAA_ARRAY r128
2482+
// GFX11: [0x1c,0x84,0x60,0xf0,0x01,0x05,0x02,0x00]
2483+
24662484
image_msaa_load v[252:255], v[252:255], s[8:15] dmask:0x4 dim:SQ_RSRC_IMG_2D_MSAA_ARRAY
24672485
// GFX11: [0x1c,0x04,0x60,0xf0,0xfc,0xfc,0x02,0x00]
24682486

@@ -2487,6 +2505,9 @@ image_msaa_load v[253:255], v[254:255], ttmp[8:15] dmask:0x4 dim:SQ_RSRC_IMG_2D_
24872505
image_sample v[5:6], v1, s[8:15], s[12:15] dmask:0x3 dim:SQ_RSRC_IMG_1D
24882506
// GFX11: [0x00,0x03,0x6c,0xf0,0x01,0x05,0x02,0x0c]
24892507

2508+
image_sample v[5:6], v1, s[8:11], s[12:15] dmask:0x3 dim:SQ_RSRC_IMG_1D r128
2509+
// GFX11: [0x00,0x83,0x6c,0xf0,0x01,0x05,0x02,0x0c]
2510+
24902511
image_sample v[5:6], v255, s[8:15], s[12:15] dmask:0x3 dim:SQ_RSRC_IMG_1D
24912512
// GFX11: [0x00,0x03,0x6c,0xf0,0xff,0x05,0x02,0x0c]
24922513

@@ -5271,6 +5292,9 @@ image_sample_o v[254:255], v[253:255], ttmp[8:15], ttmp[12:15] dmask:0x4 dim:SQ_
52715292
image_store v[1:2], v2, s[12:19] dmask:0x3 dim:SQ_RSRC_IMG_1D unorm
52725293
// GFX11: [0x80,0x03,0x18,0xf0,0x02,0x01,0x03,0x00]
52735294

5295+
image_store v[1:2], v2, s[12:15] dmask:0x3 dim:SQ_RSRC_IMG_1D unorm r128
5296+
// GFX11: [0x80,0x83,0x18,0xf0,0x02,0x01,0x03,0x00]
5297+
52745298
image_store v[1:2], v255, s[12:19] dmask:0x3 dim:SQ_RSRC_IMG_1D unorm
52755299
// GFX11: [0x80,0x03,0x18,0xf0,0xff,0x01,0x03,0x00]
52765300

0 commit comments

Comments
 (0)