[RISCV][test] Add a test for vector hasAndNot

Author: pfusik

llvm/test/CodeGen/RISCV/rvv/vandn-sdnode.ll

@@ -2567,3 +2567,24 @@ for.body:
   %exitcond.not = icmp eq i64 %indvars.iv.next, 256
   br i1 %exitcond.not, label %for.cond.cleanup, label %for.body
 }
+
+define <vscale x 1 x i8> @not_signbit_mask_nxv1i8(<vscale x 1 x i8> %a, <vscale x 1 x i8> %b) {
+; CHECK-LABEL: not_signbit_mask_nxv1i8:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e8, mf8, ta, ma
+; CHECK-NEXT:    vmsgt.vi v0, v8, -1
+; CHECK-NEXT:    vmv.v.i v8, 0
+; CHECK-NEXT:    vmerge.vvm v8, v8, v9, v0
+; CHECK-NEXT:    ret
+;
+; CHECK-ZVKB-LABEL: not_signbit_mask_nxv1i8:
+; CHECK-ZVKB:       # %bb.0:
+; CHECK-ZVKB-NEXT:    vsetvli a0, zero, e8, mf8, ta, ma
+; CHECK-ZVKB-NEXT:    vmsgt.vi v0, v8, -1
+; CHECK-ZVKB-NEXT:    vmv.v.i v8, 0
+; CHECK-ZVKB-NEXT:    vmerge.vvm v8, v8, v9, v0
+; CHECK-ZVKB-NEXT:    ret
+  %cond = icmp sgt <vscale x 1 x i8> %a, splat (i8 -1)
+  %r = select <vscale x 1 x i1> %cond, <vscale x 1 x i8> %b, <vscale x 1 x i8> zeroinitializer
+  ret <vscale x 1 x i8> %r
+}