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[AMDGPU][True16][MC] update VOPC profile with latest vop3 true16, use
f16 for fake16 format
1 parent 3268d51 commit 9bb47f7

13 files changed

+157
-105
lines changed

‎llvm/lib/Target/AMDGPU/SIInstrInfo.cpp‎

Lines changed: 3 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -7342,14 +7342,15 @@ void SIInstrInfo::moveToVALUImpl(SIInstrWorklist &Worklist,
73427342
auto NewInstr =
73437343
BuildMI(*MBB, Inst, Inst.getDebugLoc(), get(NewOpcode), CondReg)
73447344
.setMIFlags(Inst.getFlags());
7345-
if (AMDGPU::getNamedOperandIdx(NewOpcode,
7346-
AMDGPU::OpName::src0_modifiers) >= 0) {
7345+
if (AMDGPU::getNamedOperandIdx(NewOpcode, AMDGPU::OpName::src0_modifiers)) {
73477346
NewInstr
73487347
.addImm(0) // src0_modifiers
73497348
.add(Inst.getOperand(0)) // src0
73507349
.addImm(0) // src1_modifiers
73517350
.add(Inst.getOperand(1)) // src1
73527351
.addImm(0); // clamp
7352+
if (AMDGPU::hasNamedOperand(NewOpcode, AMDGPU::OpName::op_sel))
7353+
NewInstr.addImm(0); // op_sel0
73537354
} else {
73547355
NewInstr
73557356
.add(Inst.getOperand(0))

‎llvm/lib/Target/AMDGPU/SIInstructions.td‎

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -3463,7 +3463,7 @@ def : GCNPat <
34633463
SRCMODS.NONE,
34643464
(V_MOV_B64_PSEUDO (i64 0x3fefffffffffffff))),
34653465
$x,
3466-
(V_CMP_CLASS_F64_e64 SRCMODS.NONE, $x, (i32 3 /*NaN*/))))
3466+
(V_CMP_CLASS_F64_e64 SRCMODS.NONE, $x, SRCMODS.NONE, (i32 3 /*NaN*/))))
34673467
>;
34683468

34693469
} // End SubtargetPredicates = isGFX6

‎llvm/lib/Target/AMDGPU/VOPCInstructions.td‎

Lines changed: 62 additions & 37 deletions
Original file line numberDiff line numberDiff line change
@@ -192,6 +192,8 @@ class VOPC_Real <VOPC_Pseudo ps, int EncodingFamily, string asm_name = ps.Pseudo
192192

193193
// copy relevant pseudo op flags
194194
let SubtargetPredicate = ps.SubtargetPredicate;
195+
let True16Predicate = ps.True16Predicate;
196+
let OtherPredicates = ps.OtherPredicates;
195197
let AsmMatchConverter = ps.AsmMatchConverter;
196198
let Constraints = ps.Constraints;
197199
let DisableEncoding = ps.DisableEncoding;
@@ -314,7 +316,7 @@ multiclass VOPC_Pseudos <string opName,
314316
let isCommutable = 1;
315317
}
316318

317-
def _e64 : VOP3_Pseudo<opName, P, getVOPCPat64<cond, P>.ret>,
319+
def _e64 : VOP3_Pseudo<opName, P, getVOPCPat64<cond, P>.ret, /*IsVOP3P*/false, P.HasOpSel>,
318320
Commutable_REV<revOp#"_e64", !eq(revOp, opName)>,
319321
VCMPXNoSDstTable<1, opName#"_e64">,
320322
VCMPVCMPXTable<opName#"_e64"> {
@@ -373,7 +375,7 @@ multiclass VOPCX_Pseudos <string opName,
373375
let IsVCMPX = 1;
374376
}
375377

376-
def _nosdst_e64 : VOP3_Pseudo<opName#"_nosdst", P_NoSDst>,
378+
def _nosdst_e64 : VOP3_Pseudo<opName#"_nosdst", P_NoSDst, [], /*IsVOP3P*/false, P_NoSDst.HasOpSel>,
377379
Commutable_REV<revOp#"_nosdst_e64", !eq(revOp, opName)>,
378380
VCMPXNoSDstTable<0, opName#"_e64">,
379381
VCMPVCMPXTable<!subst("v_cmpx", "v_cmp", opName#"_e64")> {
@@ -801,24 +803,11 @@ defm V_CMPX_T_U64 : VOPCX_I64 <"v_cmpx_t_u64">;
801803

802804
class VOPC_Class_Profile<list<SchedReadWrite> sched, ValueType src0VT, ValueType src1VT = i32> :
803805
VOPC_Profile<sched, src0VT, src1VT> {
804-
let AsmDPP = "$src0_modifiers, $src1 $dpp_ctrl$row_mask$bank_mask$bound_ctrl";
805-
let AsmDPP16 = AsmDPP#"$fi";
806-
let InsDPP = (ins Src0ModDPP:$src0_modifiers, Src0DPP:$src0, Src1DPP:$src1, dpp_ctrl:$dpp_ctrl, DppRowMask:$row_mask, DppBankMask:$bank_mask, DppBoundCtrl:$bound_ctrl);
807-
let InsDPP16 = !con(InsDPP, (ins Dpp16FI:$fi));
808-
// DPP8 forbids modifiers and can inherit from VOPC_Profile
809-
810-
let Ins64 = (ins Src0Mod:$src0_modifiers, Src0RC64:$src0, Src1RC64:$src1);
811-
dag InsPartVOP3DPP = (ins FPVRegInputMods:$src0_modifiers, VGPRSrc_32:$src0, VCSrc_b32:$src1);
812-
let InsVOP3Base = !con(InsPartVOP3DPP, !if(HasOpSel, (ins op_sel0:$op_sel),
813-
(ins)));
814-
let AsmVOP3Base = "$sdst, $src0_modifiers, $src1";
815-
816806
let InsSDWA = (ins Src0ModSDWA:$src0_modifiers, Src0SDWA:$src0,
817807
Src1ModSDWA:$src1_modifiers, Src1SDWA:$src1,
818808
Clamp:$clamp, src0_sel:$src0_sel, src1_sel:$src1_sel);
819809

820810
let AsmSDWA = " vcc, $src0_modifiers, $src1_modifiers$clamp $src0_sel $src1_sel";
821-
let HasSrc1Mods = 0;
822811
let HasClamp = 0;
823812
let HasOMod = 0;
824813
}
@@ -837,16 +826,26 @@ multiclass VOPC_Class_Profile_t16<list<SchedReadWrite> sched> {
837826
let Src1ModDPP = getSrcModDPP_t16<Src1VT>.ret;
838827
let Src2ModDPP = getSrcModDPP_t16<Src2VT>.ret;
839828
}
840-
def _fake16 : VOPC_Class_Profile<sched, f16, i16> {
829+
def _fake16 : VOPC_Class_Profile<sched, f16, f16> {
841830
let IsTrue16 = 1;
831+
let DstRC = getVALUDstForVT_fake16<DstVT>.ret;
832+
let DstRC64 = getVALUDstForVT<DstVT>.ret;
833+
let Src0RC32 = getVOPSrc0ForVT<Src0VT, 1/*IsTrue16*/, 1/*IsFake16*/>.ret;
842834
let Src1RC32 = getVregSrcForVT<Src1VT, 1/*IsTrue16*/, 1/*IsFake16*/>.ret;
843835
let Src1RC64 = VSrc_b32;
844836
let Src0DPP = getVregSrcForVT<Src0VT, 1/*IsTrue16*/, 1/*IsFake16*/>.ret;
845837
let Src1DPP = getVregSrcForVT<Src1VT, 1/*IsTrue16*/, 1/*IsFake16*/>.ret;
846838
let Src2DPP = getVregSrcForVT<Src2VT, 1/*IsTrue16*/, 1/*IsFake16*/>.ret;
847-
let Src0ModDPP = getSrcModDPP_t16<Src0VT>.ret;
848-
let Src1ModDPP = getSrcModDPP_t16<Src1VT>.ret;
849-
let Src2ModDPP = getSrcModDPP_t16<Src2VT>.ret;
839+
let Src0ModDPP = getSrcModDPP_t16<Src0VT, 1/*IsFake16*/>.ret;
840+
let Src1ModDPP = getSrcModDPP_t16<Src1VT, 1/*IsFake16*/>.ret;
841+
let Src2ModDPP = getSrcModDPP_t16<Src2VT, 1/*IsFake16*/>.ret;
842+
let Src0VOP3DPP = VGPRSrc_32;
843+
let Src1VOP3DPP = getVOP3DPPSrcForVT<Src1VT, 1/*IsFake16*/>.ret;
844+
let Src2VOP3DPP = getVOP3DPPSrcForVT<Src2VT, 1/*IsFake16*/>.ret;
845+
let Src0ModVOP3DPP = getSrc0ModVOP3DPP<Src0VT, DstVT, 1/*IsFake16*/>.ret;
846+
let Src1ModVOP3DPP = getSrcModVOP3DPP<Src1VT, 1/*IsFake16*/>.ret;
847+
let Src2ModVOP3DPP = getSrcModVOP3DPP<Src2VT, 1/*IsFake16*/>.ret;
848+
850849
}
851850
}
852851

@@ -889,17 +888,35 @@ multiclass VOPC_Class_NoSdst_Profile_t16<list<SchedReadWrite> sched> {
889888
}
890889
}
891890

892-
class getVOPCClassPat64 <VOPProfile P> {
893-
list<dag> ret =
894-
[(set i1:$sdst,
891+
multiclass VOPCClassPat64<string inst_name> {
892+
defvar inst = !cast<VOP_Pseudo>(inst_name#"_e64");
893+
defvar P = inst.Pfl;
894+
def : GCNPat <
895+
(i1:$sdst
895896
(AMDGPUfp_class
896897
(P.Src0VT (VOP3ModsNonCanonicalizing P.Src0VT:$src0, i32:$src0_modifiers)),
897-
i32:$src1))];
898+
P.Src1VT:$src1)),
899+
(inst i32:$src0_modifiers, P.Src0VT:$src0,
900+
0 /*src1_modifiers*/, P.Src1VT:$src1)
901+
>;
898902
}
899903

904+
multiclass VOPCClassPat64_fake16<string inst_name> {
905+
defvar inst = !cast<VOP_Pseudo>(inst_name#"_fake16_e64");
906+
defvar P = inst.Pfl;
907+
def : GCNPat <
908+
(i1:$sdst
909+
(AMDGPUfp_class
910+
(P.Src0VT (VOP3ModsNonCanonicalizing P.Src0VT:$src0, i32:$src0_modifiers)),
911+
i32:$src1)),
912+
(inst i32:$src0_modifiers, P.Src0VT:$src0,
913+
0 /*src1_modifiers*/, VGPR_32:$src1)
914+
>;
915+
}
900916

901-
// Special case for class instructions which only have modifiers on
902-
// the 1st source operand.
917+
// cmp_class ignores the FP mode and faithfully reports the unmodified
918+
// source value.
919+
let ReadsModeReg = 0, mayRaiseFPException = 0 in {
903920
multiclass VOPC_Class_Pseudos <string opName, VOPC_Profile p, bit DefExec,
904921
bit DefVcc = 1> {
905922
def _e32 : VOPC_Pseudo <opName, p>,
@@ -910,7 +927,7 @@ multiclass VOPC_Class_Pseudos <string opName, VOPC_Profile p, bit DefExec,
910927
let isConvergent = DefExec;
911928
}
912929

913-
def _e64 : VOP3_Pseudo<opName, p, getVOPCClassPat64<p>.ret>,
930+
def _e64 : VOP3_Pseudo<opName, p, [], 0/*IsVOP3P*/, p.HasOpSel>,
914931
VCMPXNoSDstTable<1, opName#"_e64"> {
915932
let Defs = !if(DefExec, [EXEC], []);
916933
let SchedRW = p.Schedule;
@@ -957,7 +974,7 @@ multiclass VOPCX_Class_Pseudos <string opName,
957974
let SubtargetPredicate = HasNoSdstCMPX;
958975
}
959976

960-
def _nosdst_e64 : VOP3_Pseudo<opName#"_nosdst", P_NoSDst>,
977+
def _nosdst_e64 : VOP3_Pseudo<opName#"_nosdst", P_NoSDst, [], 0/*IsVOP3P*/, P_NoSDst.HasOpSel>,
961978
VCMPXNoSDstTable<0, opName#"_e64"> {
962979
let Defs = [EXEC];
963980
let SchedRW = P_NoSDst.Schedule;
@@ -990,6 +1007,7 @@ multiclass VOPCX_Class_Pseudos <string opName,
9901007
} // end SubtargetPredicate = isGFX11Plus
9911008
}
9921009
} // End SubtargetPredicate = HasSdstCMPX
1010+
} // End ReadsModeReg = 0, mayRaiseFPException = 0
9931011

9941012
defm VOPC_I1_F16_I16 : VOPC_Class_Profile_t16<[Write32Bit]>;
9951013
def VOPC_I1_F32_I32 : VOPC_Class_Profile<[Write32Bit], f32>;
@@ -1002,12 +1020,14 @@ def VOPC_F64_I32 : VOPC_Class_NoSdst_Profile<[Write64Bit], f64>;
10021020
multiclass VOPC_CLASS_F16 <string opName> {
10031021
let OtherPredicates = [Has16BitInsts], True16Predicate = NotHasTrue16BitInsts in {
10041022
defm NAME : VOPC_Class_Pseudos <opName, VOPC_I1_F16_I16, 0>;
1023+
defm : VOPCClassPat64<NAME>;
10051024
}
1006-
let OtherPredicates = [UseRealTrue16Insts] in {
1025+
let True16Predicate = UseRealTrue16Insts in {
10071026
defm _t16 : VOPC_Class_Pseudos <opName#"_t16", VOPC_I1_F16_I16_t16, 0>;
10081027
}
1009-
let OtherPredicates = [UseFakeTrue16Insts] in {
1028+
let True16Predicate = UseFakeTrue16Insts in {
10101029
defm _fake16 : VOPC_Class_Pseudos <opName#"_fake16", VOPC_I1_F16_I16_fake16, 0>;
1030+
defm : VOPCClassPat64_fake16<NAME>;
10111031
}
10121032
}
10131033

@@ -1023,29 +1043,29 @@ multiclass VOPCX_CLASS_F16 <string opName> {
10231043
}
10241044
}
10251045

1026-
multiclass VOPC_CLASS_F32 <string opName> :
1027-
VOPC_Class_Pseudos <opName, VOPC_I1_F32_I32, 0>;
1046+
multiclass VOPC_CLASS_F32 <string opName> {
1047+
defm NAME : VOPC_Class_Pseudos <opName, VOPC_I1_F32_I32, 0>;
1048+
defm : VOPCClassPat64<NAME>;
1049+
}
10281050

10291051
multiclass VOPCX_CLASS_F32 <string opName> :
10301052
VOPCX_Class_Pseudos <opName, VOPC_I1_F32_I32, VOPC_F32_I32>;
10311053

1032-
multiclass VOPC_CLASS_F64 <string opName> :
1033-
VOPC_Class_Pseudos <opName, VOPC_I1_F64_I32, 0>;
1054+
multiclass VOPC_CLASS_F64 <string opName> {
1055+
defm NAME : VOPC_Class_Pseudos <opName, VOPC_I1_F64_I32, 0>;
1056+
defm : VOPCClassPat64<NAME>;
1057+
}
10341058

10351059
multiclass VOPCX_CLASS_F64 <string opName> :
10361060
VOPCX_Class_Pseudos <opName, VOPC_I1_F64_I32, VOPC_F64_I32>;
10371061

1038-
// cmp_class ignores the FP mode and faithfully reports the unmodified
1039-
// source value.
1040-
let ReadsModeReg = 0, mayRaiseFPException = 0 in {
10411062
defm V_CMP_CLASS_F32 : VOPC_CLASS_F32 <"v_cmp_class_f32">;
10421063
defm V_CMPX_CLASS_F32 : VOPCX_CLASS_F32 <"v_cmpx_class_f32">;
10431064
defm V_CMP_CLASS_F64 : VOPC_CLASS_F64 <"v_cmp_class_f64">;
10441065
defm V_CMPX_CLASS_F64 : VOPCX_CLASS_F64 <"v_cmpx_class_f64">;
10451066

10461067
defm V_CMP_CLASS_F16 : VOPC_CLASS_F16 <"v_cmp_class_f16">;
10471068
defm V_CMPX_CLASS_F16 : VOPCX_CLASS_F16 <"v_cmpx_class_f16">;
1048-
} // End ReadsModeReg = 0, mayRaiseFPException = 0
10491069

10501070
//===----------------------------------------------------------------------===//
10511071
// V_ICMPIntrinsic Pattern.
@@ -1283,11 +1303,13 @@ class VOPC_DPP16<bits<8> op, VOP_DPP_Pseudo ps, string opName = ps.OpName>
12831303
: VOPC_DPP_Base<op, opName, ps.Pfl> {
12841304
let AssemblerPredicate = HasDPP16;
12851305
let SubtargetPredicate = HasDPP16;
1306+
let True16Predicate = ps.True16Predicate;
12861307
let hasSideEffects = ps.hasSideEffects;
12871308
let Defs = ps.Defs;
12881309
let SchedRW = ps.SchedRW;
12891310
let Uses = ps.Uses;
12901311
let OtherPredicates = ps.OtherPredicates;
1312+
let True16Predicate = ps.True16Predicate;
12911313
let Constraints = ps.Constraints;
12921314
}
12931315

@@ -1303,6 +1325,7 @@ class VOPC_DPP8<bits<8> op, VOPC_Pseudo ps, string opName = ps.OpName>
13031325
let SchedRW = ps.SchedRW;
13041326
let Uses = ps.Uses;
13051327
let OtherPredicates = ps.OtherPredicates;
1328+
let True16Predicate = ps.True16Predicate;
13061329
let Constraints = "";
13071330
}
13081331

@@ -1333,6 +1356,7 @@ class VOPC64_DPP16<bits<10> op, VOP_DPP_Pseudo ps, string opName = ps.OpName>
13331356
: VOPC64_DPP_Base<op, opName, ps.Pfl> {
13341357
let AssemblerPredicate = HasDPP16;
13351358
let SubtargetPredicate = HasDPP16;
1359+
let True16Predicate = ps.True16Predicate;
13361360
let hasSideEffects = ps.hasSideEffects;
13371361
let Defs = ps.Defs;
13381362
let SchedRW = ps.SchedRW;
@@ -1375,6 +1399,7 @@ class VOPC64_DPP8<bits<10> op, VOP_Pseudo ps, string opName = ps.OpName>
13751399
let SchedRW = ps.SchedRW;
13761400
let Uses = ps.Uses;
13771401
let OtherPredicates = ps.OtherPredicates;
1402+
let True16Predicate = ps.True16Predicate;
13781403
}
13791404

13801405
class VOPC64_DPP8_Dst<bits<10> op, VOP_Pseudo ps, string opName = ps.OpName>

‎llvm/lib/Target/AMDGPU/VOPInstructions.td‎

Lines changed: 5 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -1873,15 +1873,16 @@ include "VOPDInstructions.td"
18731873

18741874
class ClassPat<Instruction inst, ValueType vt> : GCNPat <
18751875
(is_fpclass (vt (VOP3ModsNonCanonicalizing vt:$src0, i32:$src0_mods)), (i32 timm:$mask)),
1876-
(inst i32:$src0_mods, vt:$src0, (V_MOV_B32_e32 timm:$mask))
1876+
(inst i32:$src0_mods, vt:$src0, SRCMODS.NONE, (V_MOV_B32_e32 timm:$mask))
18771877
>;
18781878

18791879
def : ClassPat<V_CMP_CLASS_F16_e64, f16> {
1880-
let OtherPredicates = [NotHasTrue16BitInsts, Has16BitInsts];
1880+
let OtherPredicates = [Has16BitInsts];
1881+
let True16Predicate = NotHasTrue16BitInsts;
18811882
}
18821883

1883-
def : ClassPat<V_CMP_CLASS_F16_t16_e64, f16> {
1884-
let OtherPredicates = [HasTrue16BitInsts];
1884+
def : ClassPat<V_CMP_CLASS_F16_fake16_e64, f16> {
1885+
let True16Predicate = UseFakeTrue16Insts;
18851886
}
18861887

18871888
def : ClassPat<V_CMP_CLASS_F32_e64, f32>;

‎llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-amdgcn.class.mir‎

Lines changed: 18 additions & 12 deletions
Original file line numberDiff line numberDiff line change
@@ -16,14 +16,15 @@ body: |
1616
; WAVE64-NEXT: {{ $}}
1717
; WAVE64-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
1818
; WAVE64-NEXT: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr0
19-
; WAVE64-NEXT: [[V_CMP_CLASS_F32_e64_:%[0-9]+]]:sreg_64_xexec = V_CMP_CLASS_F32_e64 0, [[COPY]], [[COPY1]], implicit $exec
19+
; WAVE64-NEXT: [[V_CMP_CLASS_F32_e64_:%[0-9]+]]:sreg_64_xexec = V_CMP_CLASS_F32_e64 0, [[COPY]], 0, [[COPY1]], implicit $exec
2020
; WAVE64-NEXT: S_ENDPGM 0, implicit [[V_CMP_CLASS_F32_e64_]]
21+
;
2122
; WAVE32-LABEL: name: class_s32_vcc_sv
2223
; WAVE32: liveins: $sgpr0, $vgpr0
2324
; WAVE32-NEXT: {{ $}}
2425
; WAVE32-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
2526
; WAVE32-NEXT: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr0
26-
; WAVE32-NEXT: [[V_CMP_CLASS_F32_e64_:%[0-9]+]]:sreg_32_xm0_xexec = V_CMP_CLASS_F32_e64 0, [[COPY]], [[COPY1]], implicit $exec
27+
; WAVE32-NEXT: [[V_CMP_CLASS_F32_e64_:%[0-9]+]]:sreg_32_xm0_xexec = V_CMP_CLASS_F32_e64 0, [[COPY]], 0, [[COPY1]], implicit $exec
2728
; WAVE32-NEXT: S_ENDPGM 0, implicit [[V_CMP_CLASS_F32_e64_]]
2829
%0:sgpr(s32) = COPY $sgpr0
2930
%1:vgpr(s32) = COPY $vgpr0
@@ -45,14 +46,15 @@ body: |
4546
; WAVE64-NEXT: {{ $}}
4647
; WAVE64-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
4748
; WAVE64-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr0
48-
; WAVE64-NEXT: [[V_CMP_CLASS_F32_e64_:%[0-9]+]]:sreg_64_xexec = V_CMP_CLASS_F32_e64 0, [[COPY]], [[COPY1]], implicit $exec
49+
; WAVE64-NEXT: [[V_CMP_CLASS_F32_e64_:%[0-9]+]]:sreg_64_xexec = V_CMP_CLASS_F32_e64 0, [[COPY]], 0, [[COPY1]], implicit $exec
4950
; WAVE64-NEXT: S_ENDPGM 0, implicit [[V_CMP_CLASS_F32_e64_]]
51+
;
5052
; WAVE32-LABEL: name: class_s32_vcc_vs
5153
; WAVE32: liveins: $sgpr0, $vgpr0
5254
; WAVE32-NEXT: {{ $}}
5355
; WAVE32-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
5456
; WAVE32-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr0
55-
; WAVE32-NEXT: [[V_CMP_CLASS_F32_e64_:%[0-9]+]]:sreg_32_xm0_xexec = V_CMP_CLASS_F32_e64 0, [[COPY]], [[COPY1]], implicit $exec
57+
; WAVE32-NEXT: [[V_CMP_CLASS_F32_e64_:%[0-9]+]]:sreg_32_xm0_xexec = V_CMP_CLASS_F32_e64 0, [[COPY]], 0, [[COPY1]], implicit $exec
5658
; WAVE32-NEXT: S_ENDPGM 0, implicit [[V_CMP_CLASS_F32_e64_]]
5759
%0:vgpr(s32) = COPY $vgpr0
5860
%1:sgpr(s32) = COPY $sgpr0
@@ -74,14 +76,15 @@ body: |
7476
; WAVE64-NEXT: {{ $}}
7577
; WAVE64-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
7678
; WAVE64-NEXT: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
77-
; WAVE64-NEXT: [[V_CMP_CLASS_F32_e64_:%[0-9]+]]:sreg_64_xexec = V_CMP_CLASS_F32_e64 0, [[COPY]], [[COPY1]], implicit $exec
79+
; WAVE64-NEXT: [[V_CMP_CLASS_F32_e64_:%[0-9]+]]:sreg_64_xexec = V_CMP_CLASS_F32_e64 0, [[COPY]], 0, [[COPY1]], implicit $exec
7880
; WAVE64-NEXT: S_ENDPGM 0, implicit [[V_CMP_CLASS_F32_e64_]]
81+
;
7982
; WAVE32-LABEL: name: class_s32_vcc_vv
8083
; WAVE32: liveins: $vgpr0, $vgpr1
8184
; WAVE32-NEXT: {{ $}}
8285
; WAVE32-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
8386
; WAVE32-NEXT: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
84-
; WAVE32-NEXT: [[V_CMP_CLASS_F32_e64_:%[0-9]+]]:sreg_32_xm0_xexec = V_CMP_CLASS_F32_e64 0, [[COPY]], [[COPY1]], implicit $exec
87+
; WAVE32-NEXT: [[V_CMP_CLASS_F32_e64_:%[0-9]+]]:sreg_32_xm0_xexec = V_CMP_CLASS_F32_e64 0, [[COPY]], 0, [[COPY1]], implicit $exec
8588
; WAVE32-NEXT: S_ENDPGM 0, implicit [[V_CMP_CLASS_F32_e64_]]
8689
%0:vgpr(s32) = COPY $vgpr0
8790
%1:vgpr(s32) = COPY $vgpr1
@@ -103,14 +106,15 @@ body: |
103106
; WAVE64-NEXT: {{ $}}
104107
; WAVE64-NEXT: [[COPY:%[0-9]+]]:sreg_64 = COPY $sgpr0_sgpr1
105108
; WAVE64-NEXT: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr0
106-
; WAVE64-NEXT: [[V_CMP_CLASS_F64_e64_:%[0-9]+]]:sreg_64_xexec = V_CMP_CLASS_F64_e64 0, [[COPY]], [[COPY1]], implicit $exec
109+
; WAVE64-NEXT: [[V_CMP_CLASS_F64_e64_:%[0-9]+]]:sreg_64_xexec = V_CMP_CLASS_F64_e64 0, [[COPY]], 0, [[COPY1]], implicit $exec
107110
; WAVE64-NEXT: S_ENDPGM 0, implicit [[V_CMP_CLASS_F64_e64_]]
111+
;
108112
; WAVE32-LABEL: name: class_s64_vcc_sv
109113
; WAVE32: liveins: $sgpr0_sgpr1, $vgpr0
110114
; WAVE32-NEXT: {{ $}}
111115
; WAVE32-NEXT: [[COPY:%[0-9]+]]:sreg_64 = COPY $sgpr0_sgpr1
112116
; WAVE32-NEXT: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr0
113-
; WAVE32-NEXT: [[V_CMP_CLASS_F64_e64_:%[0-9]+]]:sreg_32_xm0_xexec = V_CMP_CLASS_F64_e64 0, [[COPY]], [[COPY1]], implicit $exec
117+
; WAVE32-NEXT: [[V_CMP_CLASS_F64_e64_:%[0-9]+]]:sreg_32_xm0_xexec = V_CMP_CLASS_F64_e64 0, [[COPY]], 0, [[COPY1]], implicit $exec
114118
; WAVE32-NEXT: S_ENDPGM 0, implicit [[V_CMP_CLASS_F64_e64_]]
115119
%0:sgpr(s64) = COPY $sgpr0_sgpr1
116120
%1:vgpr(s32) = COPY $vgpr0
@@ -133,14 +137,15 @@ body: |
133137
; WAVE64-NEXT: {{ $}}
134138
; WAVE64-NEXT: [[COPY:%[0-9]+]]:vreg_64 = COPY $vgpr0_vgpr1
135139
; WAVE64-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr0
136-
; WAVE64-NEXT: [[V_CMP_CLASS_F64_e64_:%[0-9]+]]:sreg_64_xexec = V_CMP_CLASS_F64_e64 0, [[COPY]], [[COPY1]], implicit $exec
140+
; WAVE64-NEXT: [[V_CMP_CLASS_F64_e64_:%[0-9]+]]:sreg_64_xexec = V_CMP_CLASS_F64_e64 0, [[COPY]], 0, [[COPY1]], implicit $exec
137141
; WAVE64-NEXT: S_ENDPGM 0, implicit [[V_CMP_CLASS_F64_e64_]]
142+
;
138143
; WAVE32-LABEL: name: class_s64_vcc_vs
139144
; WAVE32: liveins: $sgpr0_sgpr1, $vgpr0
140145
; WAVE32-NEXT: {{ $}}
141146
; WAVE32-NEXT: [[COPY:%[0-9]+]]:vreg_64 = COPY $vgpr0_vgpr1
142147
; WAVE32-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr0
143-
; WAVE32-NEXT: [[V_CMP_CLASS_F64_e64_:%[0-9]+]]:sreg_32_xm0_xexec = V_CMP_CLASS_F64_e64 0, [[COPY]], [[COPY1]], implicit $exec
148+
; WAVE32-NEXT: [[V_CMP_CLASS_F64_e64_:%[0-9]+]]:sreg_32_xm0_xexec = V_CMP_CLASS_F64_e64 0, [[COPY]], 0, [[COPY1]], implicit $exec
144149
; WAVE32-NEXT: S_ENDPGM 0, implicit [[V_CMP_CLASS_F64_e64_]]
145150
%0:vgpr(s64) = COPY $vgpr0_vgpr1
146151
%1:sgpr(s32) = COPY $sgpr0
@@ -163,14 +168,15 @@ body: |
163168
; WAVE64-NEXT: {{ $}}
164169
; WAVE64-NEXT: [[COPY:%[0-9]+]]:vreg_64 = COPY $vgpr0_vgpr1
165170
; WAVE64-NEXT: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr2
166-
; WAVE64-NEXT: [[V_CMP_CLASS_F64_e64_:%[0-9]+]]:sreg_64_xexec = V_CMP_CLASS_F64_e64 0, [[COPY]], [[COPY1]], implicit $exec
171+
; WAVE64-NEXT: [[V_CMP_CLASS_F64_e64_:%[0-9]+]]:sreg_64_xexec = V_CMP_CLASS_F64_e64 0, [[COPY]], 0, [[COPY1]], implicit $exec
167172
; WAVE64-NEXT: S_ENDPGM 0, implicit [[V_CMP_CLASS_F64_e64_]]
173+
;
168174
; WAVE32-LABEL: name: class_s64_vcc_vv
169175
; WAVE32: liveins: $vgpr0_vgpr1, $vgpr2
170176
; WAVE32-NEXT: {{ $}}
171177
; WAVE32-NEXT: [[COPY:%[0-9]+]]:vreg_64 = COPY $vgpr0_vgpr1
172178
; WAVE32-NEXT: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr2
173-
; WAVE32-NEXT: [[V_CMP_CLASS_F64_e64_:%[0-9]+]]:sreg_32_xm0_xexec = V_CMP_CLASS_F64_e64 0, [[COPY]], [[COPY1]], implicit $exec
179+
; WAVE32-NEXT: [[V_CMP_CLASS_F64_e64_:%[0-9]+]]:sreg_32_xm0_xexec = V_CMP_CLASS_F64_e64 0, [[COPY]], 0, [[COPY1]], implicit $exec
174180
; WAVE32-NEXT: S_ENDPGM 0, implicit [[V_CMP_CLASS_F64_e64_]]
175181
%0:vgpr(s64) = COPY $vgpr0_vgpr1
176182
%1:vgpr(s32) = COPY $vgpr2

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