Update

Author: lialan

mlir/include/mlir/Dialect/AMDGPU/IR/AMDGPU.td

@@ -898,16 +898,6 @@ def AMDGPU_GatherToLDSOp :
   let hasVerifier = 1;
 }
 
-def F8Types : AnyTypeOf<[
-  F8E8M0FNU,      // 8 exponent, 0 mantissa
-  F8E5M2,         // 5 exponent, 2 mantissa
-  F8E5M2FNUZ,     // 5 exponent, 2 mantissa
-  F8E4M3,         // 4 exponent, 3 mantissa
-  F8E4M3FN,       // 4 exponent, 3 mantissa
-  F8E4M3B11FNUZ,  // 4 exponent, 3 mantissa (with bias 11)
-  F8E3M4          // 3 exponent, 4 mantissa
-]>;
-
 def AMDGPU_TransposeLoadOp :
     AMDGPU_Op<"transpose_load", [SameVariadicOperandSize]>,
     Arguments<(ins Arg<AnyMemRef, "buffer to transpose load from", [MemRead]>:$src, Variadic<Index>:$srcIndices)>,

mlir/lib/Conversion/AMDGPUToROCDL/AMDGPUToROCDL.cpp

@@ -1110,7 +1110,7 @@ struct TransposeLoadOpLowering
   LogicalResult
   matchAndRewrite(TransposeLoadOp op, TransposeLoadOpAdaptor adaptor,
                   ConversionPatternRewriter &rewriter) const override {
-    if (chipset < kGfx950)
+    if (chipset != kGfx950)
       return op.emitOpError("Non-gfx950 chipset not supported");
 
     Location loc = op.getLoc();

mlir/lib/Dialect/AMDGPU/IR/AMDGPUDialect.cpp

@@ -24,6 +24,7 @@
 #include "mlir/IR/OpImplementation.h"
 #include "mlir/IR/PatternMatch.h"
 #include "mlir/IR/TypeUtilities.h"
+#include "llvm/ADT/DenseMap.h"
 #include "llvm/ADT/TypeSwitch.h"
 
 #include <limits>
@@ -534,10 +535,11 @@ LogicalResult TransposeLoadOp::verify() {
   if (!transferType)
     return emitOpError("destination type must be a vector type");
   size_t numElements = transferType.getNumElements();
-  size_t elementTypeSize = transferType.getElementType().getIntOrFloatBitWidth();
+  size_t elementTypeSize =
+      transferType.getElementType().getIntOrFloatBitWidth();
 
   // ElementSize -> NumElements
-  const std::map<size_t, size_t> KValidLoadSizeMap = {
+  const llvm::SmallDenseMap<size_t, size_t> KValidLoadSizeMap = {
       {4, 16},
       {32, 3}, // 6-bit element loads use casted vector<3xi32>
       {8, 8},