We read every piece of feedback, and take your input very seriously.
To see all available qualifiers, see our documentation.
There was an error while loading. Please reload this page.
1 parent bbda25d commit 9becf6fCopy full SHA for 9becf6f
llvm/include/llvm/CodeGen/GlobalISel/GenericMachineInstrs.h
@@ -800,6 +800,18 @@ class GInsertVectorElement : public GenericMachineInstr {
800
}
801
};
802
803
+/// Represents a insert subvector.
804
+class GInsertSubvector : public GenericMachineInstr {
805
+public:
806
+ Register getBigVec() const { return getOperand(1).getReg(); }
807
+ Register getSubVec() const { return getOperand(1).getReg(); }
808
+ uint64_t getIndexImm() const { return getOperand(3).getImm(); }
809
+
810
+ static bool classof(const MachineInstr *MI) {
811
+ return MI->getOpcode() == TargetOpcode::G_INSERT_SUBVECTOR;
812
+ }
813
+};
814
815
/// Represents a freeze.
816
class GFreeze : public GenericMachineInstr {
817
public:
0 commit comments