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[RISCV][VLOPT] Add support for Widening Floating-Point Fused Multiply-Add Instructions
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2 files changed

+33
-20
lines changed

2 files changed

+33
-20
lines changed

llvm/lib/Target/RISCV/RISCVVLOptimizer.cpp

Lines changed: 13 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -545,6 +545,8 @@ getOperandLog2EEW(const MachineOperand &MO, const MachineRegisterInfo *MRI) {
545545
case RISCV::VFWMSAC_VV:
546546
case RISCV::VFWNMSAC_VF:
547547
case RISCV::VFWNMSAC_VV:
548+
case RISCV::VFWMACCBF16_VV:
549+
case RISCV::VFWMACCBF16_VF:
548550
// Vector Widening Floating-Point Add/Subtract Instructions
549551
// Dest EEW=2*SEW. Source EEW=SEW.
550552
case RISCV::VFWADD_VV:
@@ -1050,6 +1052,17 @@ static bool isSupportedInstr(const MachineInstr &MI) {
10501052
case RISCV::VFMSUB_VF:
10511053
case RISCV::VFNMSUB_VV:
10521054
case RISCV::VFNMSUB_VF:
1055+
// Vector Widening Floating-Point Fused Multiply-Add Instructions
1056+
case RISCV::VFWMACC_VV:
1057+
case RISCV::VFWMACC_VF:
1058+
case RISCV::VFWNMACC_VV:
1059+
case RISCV::VFWNMACC_VF:
1060+
case RISCV::VFWMSAC_VV:
1061+
case RISCV::VFWMSAC_VF:
1062+
case RISCV::VFWNMSAC_VV:
1063+
case RISCV::VFWNMSAC_VF:
1064+
case RISCV::VFWMACCBF16_VV:
1065+
case RISCV::VFWMACCBF16_VF:
10531066
// Vector Floating-Point MIN/MAX Instructions
10541067
case RISCV::VFMIN_VF:
10551068
case RISCV::VFMIN_VV:

llvm/test/CodeGen/RISCV/rvv/vl-opt-instrs.ll

Lines changed: 20 additions & 20 deletions
Original file line numberDiff line numberDiff line change
@@ -4363,9 +4363,9 @@ define <vscale x 4 x double> @vfwmacc_vv(<vscale x 4 x double> %a, <vscale x 4 x
43634363
;
43644364
; VLOPT-LABEL: vfwmacc_vv:
43654365
; VLOPT: # %bb.0:
4366-
; VLOPT-NEXT: vsetvli a1, zero, e32, m2, tu, ma
4366+
; VLOPT-NEXT: vsetvli zero, a0, e32, m2, tu, ma
43674367
; VLOPT-NEXT: vfwmacc.vv v8, v12, v14
4368-
; VLOPT-NEXT: vsetvli zero, a0, e64, m4, ta, ma
4368+
; VLOPT-NEXT: vsetvli zero, zero, e64, m4, ta, ma
43694369
; VLOPT-NEXT: vfadd.vv v8, v8, v16
43704370
; VLOPT-NEXT: ret
43714371
%1 = call <vscale x 4 x double> @llvm.riscv.vfwmacc(<vscale x 4 x double> %a, <vscale x 4 x float> %b, <vscale x 4 x float> %c, iXLen 7, iXLen -1, iXLen 0)
@@ -4384,9 +4384,9 @@ define <vscale x 4 x double> @vfwmacc_vf(<vscale x 4 x double> %a, float %b, <vs
43844384
;
43854385
; VLOPT-LABEL: vfwmacc_vf:
43864386
; VLOPT: # %bb.0:
4387-
; VLOPT-NEXT: vsetvli a1, zero, e32, m2, tu, ma
4387+
; VLOPT-NEXT: vsetvli zero, a0, e32, m2, tu, ma
43884388
; VLOPT-NEXT: vfwmacc.vf v8, fa0, v12
4389-
; VLOPT-NEXT: vsetvli zero, a0, e64, m4, ta, ma
4389+
; VLOPT-NEXT: vsetvli zero, zero, e64, m4, ta, ma
43904390
; VLOPT-NEXT: vfadd.vv v8, v8, v16
43914391
; VLOPT-NEXT: ret
43924392
%1 = call <vscale x 4 x double> @llvm.riscv.vfwmacc(<vscale x 4 x double> %a, float %b, <vscale x 4 x float> %c, iXLen 7, iXLen -1, iXLen 0)
@@ -4405,9 +4405,9 @@ define <vscale x 4 x double> @vfwnmacc_vv(<vscale x 4 x double> %a, <vscale x 4
44054405
;
44064406
; VLOPT-LABEL: vfwnmacc_vv:
44074407
; VLOPT: # %bb.0:
4408-
; VLOPT-NEXT: vsetvli a1, zero, e32, m2, tu, ma
4408+
; VLOPT-NEXT: vsetvli zero, a0, e32, m2, tu, ma
44094409
; VLOPT-NEXT: vfwnmacc.vv v8, v12, v14
4410-
; VLOPT-NEXT: vsetvli zero, a0, e64, m4, ta, ma
4410+
; VLOPT-NEXT: vsetvli zero, zero, e64, m4, ta, ma
44114411
; VLOPT-NEXT: vfadd.vv v8, v8, v16
44124412
; VLOPT-NEXT: ret
44134413
%1 = call <vscale x 4 x double> @llvm.riscv.vfwnmacc(<vscale x 4 x double> %a, <vscale x 4 x float> %b, <vscale x 4 x float> %c, iXLen 7, iXLen -1, iXLen 0)
@@ -4426,9 +4426,9 @@ define <vscale x 4 x double> @vfwnmacc_vf(<vscale x 4 x double> %a, float %b, <v
44264426
;
44274427
; VLOPT-LABEL: vfwnmacc_vf:
44284428
; VLOPT: # %bb.0:
4429-
; VLOPT-NEXT: vsetvli a1, zero, e32, m2, tu, ma
4429+
; VLOPT-NEXT: vsetvli zero, a0, e32, m2, tu, ma
44304430
; VLOPT-NEXT: vfwnmacc.vf v8, fa0, v12
4431-
; VLOPT-NEXT: vsetvli zero, a0, e64, m4, ta, ma
4431+
; VLOPT-NEXT: vsetvli zero, zero, e64, m4, ta, ma
44324432
; VLOPT-NEXT: vfadd.vv v8, v8, v16
44334433
; VLOPT-NEXT: ret
44344434
%1 = call <vscale x 4 x double> @llvm.riscv.vfwnmacc(<vscale x 4 x double> %a, float %b, <vscale x 4 x float> %c, iXLen 7, iXLen -1, iXLen 0)
@@ -4447,9 +4447,9 @@ define <vscale x 4 x double> @vfwmsac_vv(<vscale x 4 x double> %a, <vscale x 4 x
44474447
;
44484448
; VLOPT-LABEL: vfwmsac_vv:
44494449
; VLOPT: # %bb.0:
4450-
; VLOPT-NEXT: vsetvli a1, zero, e32, m2, tu, ma
4450+
; VLOPT-NEXT: vsetvli zero, a0, e32, m2, tu, ma
44514451
; VLOPT-NEXT: vfwmsac.vv v8, v12, v14
4452-
; VLOPT-NEXT: vsetvli zero, a0, e64, m4, ta, ma
4452+
; VLOPT-NEXT: vsetvli zero, zero, e64, m4, ta, ma
44534453
; VLOPT-NEXT: vfadd.vv v8, v8, v16
44544454
; VLOPT-NEXT: ret
44554455
%1 = call <vscale x 4 x double> @llvm.riscv.vfwmsac(<vscale x 4 x double> %a, <vscale x 4 x float> %b, <vscale x 4 x float> %c, iXLen 7, iXLen -1, iXLen 0)
@@ -4468,9 +4468,9 @@ define <vscale x 4 x double> @vfwmsac_vf(<vscale x 4 x double> %a, float %b, <vs
44684468
;
44694469
; VLOPT-LABEL: vfwmsac_vf:
44704470
; VLOPT: # %bb.0:
4471-
; VLOPT-NEXT: vsetvli a1, zero, e32, m2, tu, ma
4471+
; VLOPT-NEXT: vsetvli zero, a0, e32, m2, tu, ma
44724472
; VLOPT-NEXT: vfwmsac.vf v8, fa0, v12
4473-
; VLOPT-NEXT: vsetvli zero, a0, e64, m4, ta, ma
4473+
; VLOPT-NEXT: vsetvli zero, zero, e64, m4, ta, ma
44744474
; VLOPT-NEXT: vfadd.vv v8, v8, v16
44754475
; VLOPT-NEXT: ret
44764476
%1 = call <vscale x 4 x double> @llvm.riscv.vfwmsac(<vscale x 4 x double> %a, float %b, <vscale x 4 x float> %c, iXLen 7, iXLen -1, iXLen 0)
@@ -4489,9 +4489,9 @@ define <vscale x 4 x double> @vfwnmsac_vv(<vscale x 4 x double> %a, <vscale x 4
44894489
;
44904490
; VLOPT-LABEL: vfwnmsac_vv:
44914491
; VLOPT: # %bb.0:
4492-
; VLOPT-NEXT: vsetvli a1, zero, e32, m2, tu, ma
4492+
; VLOPT-NEXT: vsetvli zero, a0, e32, m2, tu, ma
44934493
; VLOPT-NEXT: vfwnmsac.vv v8, v12, v14
4494-
; VLOPT-NEXT: vsetvli zero, a0, e64, m4, ta, ma
4494+
; VLOPT-NEXT: vsetvli zero, zero, e64, m4, ta, ma
44954495
; VLOPT-NEXT: vfadd.vv v8, v8, v16
44964496
; VLOPT-NEXT: ret
44974497
%1 = call <vscale x 4 x double> @llvm.riscv.vfwnmsac(<vscale x 4 x double> %a, <vscale x 4 x float> %b, <vscale x 4 x float> %c, iXLen 7, iXLen -1, iXLen 0)
@@ -4510,9 +4510,9 @@ define <vscale x 4 x double> @vfwnmsac_vf(<vscale x 4 x double> %a, float %b, <v
45104510
;
45114511
; VLOPT-LABEL: vfwnmsac_vf:
45124512
; VLOPT: # %bb.0:
4513-
; VLOPT-NEXT: vsetvli a1, zero, e32, m2, tu, ma
4513+
; VLOPT-NEXT: vsetvli zero, a0, e32, m2, tu, ma
45144514
; VLOPT-NEXT: vfwnmsac.vf v8, fa0, v12
4515-
; VLOPT-NEXT: vsetvli zero, a0, e64, m4, ta, ma
4515+
; VLOPT-NEXT: vsetvli zero, zero, e64, m4, ta, ma
45164516
; VLOPT-NEXT: vfadd.vv v8, v8, v16
45174517
; VLOPT-NEXT: ret
45184518
%1 = call <vscale x 4 x double> @llvm.riscv.vfwnmsac(<vscale x 4 x double> %a, float %b, <vscale x 4 x float> %c, iXLen 7, iXLen -1, iXLen 0)
@@ -4531,9 +4531,9 @@ define <vscale x 4 x float> @vfwmaccbf16_vv(<vscale x 4 x float> %a, <vscale x 4
45314531
;
45324532
; VLOPT-LABEL: vfwmaccbf16_vv:
45334533
; VLOPT: # %bb.0:
4534-
; VLOPT-NEXT: vsetvli a1, zero, e16, m1, tu, ma
4534+
; VLOPT-NEXT: vsetvli zero, a0, e16, m1, tu, ma
45354535
; VLOPT-NEXT: vfwmaccbf16.vv v8, v10, v11
4536-
; VLOPT-NEXT: vsetvli zero, a0, e32, m2, ta, ma
4536+
; VLOPT-NEXT: vsetvli zero, zero, e32, m2, ta, ma
45374537
; VLOPT-NEXT: vfadd.vv v8, v8, v12
45384538
; VLOPT-NEXT: ret
45394539
%1 = call <vscale x 4 x float> @llvm.riscv.vfwmaccbf16(<vscale x 4 x float> %a, <vscale x 4 x bfloat> %b, <vscale x 4 x bfloat> %c, iXLen 7, iXLen -1, iXLen 0)
@@ -4552,9 +4552,9 @@ define <vscale x 4 x float> @vfwmaccbf16_vf(<vscale x 4 x float> %a, bfloat %b,
45524552
;
45534553
; VLOPT-LABEL: vfwmaccbf16_vf:
45544554
; VLOPT: # %bb.0:
4555-
; VLOPT-NEXT: vsetvli a1, zero, e16, m1, tu, ma
4555+
; VLOPT-NEXT: vsetvli zero, a0, e16, m1, tu, ma
45564556
; VLOPT-NEXT: vfwmaccbf16.vf v8, fa0, v10
4557-
; VLOPT-NEXT: vsetvli zero, a0, e32, m2, ta, ma
4557+
; VLOPT-NEXT: vsetvli zero, zero, e32, m2, ta, ma
45584558
; VLOPT-NEXT: vfadd.vv v8, v8, v12
45594559
; VLOPT-NEXT: ret
45604560
%1 = call <vscale x 4 x float> @llvm.riscv.vfwmaccbf16(<vscale x 4 x float> %a, bfloat %b, <vscale x 4 x bfloat> %c, iXLen 7, iXLen -1, iXLen 0)

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