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[AArch64][llvm] Armv9.7-A: Add support for new Advanced SIMD (Neon) instructions
Add support for new Advanced SIMD (Neon) instructions: - FDOT (half-precision to single-precision, by element) - FDOT (half-precision to single-precision, vector) - FMMLA (half-precision, non-widening) - FMMLA (widening, half-precision to single-precision) as documented here: * https://developer.arm.com/documentation/ddi0602/2025-09/ * https://developer.arm.com/documentation/109697/2025_09/2025-Architecture-Extensions Co-authored-by: Kerry McLaughlin <[email protected]> Co-authored-by: Caroline Concatto <[email protected]> Co-authored-by: Virginia Cangelosi <[email protected]>
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‎clang/test/Driver/print-supported-extensions-aarch64.c‎

Lines changed: 2 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -18,6 +18,8 @@
1818
// CHECK-NEXT: d128 FEAT_D128, FEAT_LVA3, FEAT_SYSREG128, FEAT_SYSINSTR128 Enable Armv9.4-A 128-bit Page Table Descriptors, System Registers and instructions
1919
// CHECK-NEXT: dit FEAT_DIT Enable Armv8.4-A Data Independent Timing instructions
2020
// CHECK-NEXT: dotprod FEAT_DotProd Enable dot product support
21+
// CHECK-NEXT: f16f32dot FEAT_F16F32DOT Enable Armv9.7-A Advanced SIMD half-precision dot product accumulate to single-precision
22+
// CHECK-NEXT: f16f32mm FEAT_F16F32MM Enable Armv9.7-A Advanced SIMD half-precision matrix multiply-accumulate to single-precision
2123
// CHECK-NEXT: f16mm FEAT_F16MM Enable Armv9.7-A non-widening half-precision matrix multiply-accumulate
2224
// CHECK-NEXT: f32mm FEAT_F32MM Enable Matrix Multiply FP32 Extension
2325
// CHECK-NEXT: f64mm FEAT_F64MM Enable Matrix Multiply FP64 Extension

‎llvm/lib/Target/AArch64/AArch64Features.td‎

Lines changed: 6 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -619,6 +619,12 @@ def FeatureSVE_B16MM : ExtensionWithMArch<"sve-b16mm", "SVE_B16MM", "FEAT_SVE_B1
619619
def FeatureF16MM : ExtensionWithMArch<"f16mm", "F16MM", "FEAT_F16MM",
620620
"Enable Armv9.7-A non-widening half-precision matrix multiply-accumulate", [FeatureFullFP16]>;
621621

622+
def FeatureF16F32DOT : ExtensionWithMArch<"f16f32dot", "F16F32DOT", "FEAT_F16F32DOT",
623+
"Enable Armv9.7-A Advanced SIMD half-precision dot product accumulate to single-precision", [FeatureNEON, FeatureFullFP16]>;
624+
625+
def FeatureF16F32MM : ExtensionWithMArch<"f16f32mm", "F16F32MM", "FEAT_F16F32MM",
626+
"Enable Armv9.7-A Advanced SIMD half-precision matrix multiply-accumulate to single-precision", [FeatureNEON, FeatureFullFP16]>;
627+
622628
//===----------------------------------------------------------------------===//
623629
// Other Features
624630
//===----------------------------------------------------------------------===//

‎llvm/lib/Target/AArch64/AArch64InstrFormats.td‎

Lines changed: 40 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -1166,6 +1166,21 @@ def timm32_0_15 : Operand<i32>, TImmLeaf<i32, [{
11661166
let ParserMatchClass = Imm0_15Operand;
11671167
}
11681168

1169+
// timm32_1_16 predicate - True if the 32-bit immediate is in the range [1,16]
1170+
def timm32_1_16 : Operand<i32>, TImmLeaf<i32, [{
1171+
return ((uint32_t)Imm > 0 && (uint32_t)Imm < 17);
1172+
}]> {
1173+
let ParserMatchClass = Imm1_16Operand;
1174+
}
1175+
1176+
// timm32_1_8 predicate - True if the 32-bit immediate is in the range [1,8]
1177+
def timm32_1_8 : Operand<i32>, TImmLeaf<i32, [{
1178+
return ((uint32_t)Imm > 0 && (uint32_t)Imm < 9);
1179+
}]> {
1180+
let ParserMatchClass = Imm1_8Operand;
1181+
}
1182+
1183+
11691184
// timm32_0_31 predicate - True if the 32-bit immediate is in the range [0,31]
11701185
def timm32_0_31 : Operand<i32>, TImmLeaf<i32, [{
11711186
return ((uint32_t)Imm) < 32;
@@ -6538,8 +6553,7 @@ multiclass SIMDThreeSameVectorFML<bit U, bit b13, bits<3> size, string asm,
65386553
}
65396554

65406555
multiclass SIMDThreeSameVectorMLA<bit Q, string asm, SDPatternOperator op> {
6541-
6542-
def v8f16 : BaseSIMDThreeSameVectorDot<Q, 0b0, 0b11, 0b1111, asm, ".8h", ".16b",
6556+
def v16f8 : BaseSIMDThreeSameVectorDot<Q, 0b0, 0b11, 0b1111, asm, ".8h", ".16b",
65436557
V128, v8f16, v16i8, op>;
65446558
}
65456559

@@ -6548,6 +6562,23 @@ multiclass SIMDThreeSameVectorMLAL<bit Q, bits<2> sz, string asm, SDPatternOpera
65486562
V128, v4f32, v16i8, op>;
65496563
}
65506564

6565+
multiclass SIMDThreeSameVectorFMLA<string asm> {
6566+
def v8f16tov8f16 : BaseSIMDThreeSameVectorDot<0b1, 0b0, 0b11, 0b1101, asm, ".8h", ".8h",
6567+
V128, v8f16, v8f16, null_frag>;
6568+
}
6569+
6570+
multiclass SIMDThreeSameVectorFMLAWiden<string asm> {
6571+
def v8f16tov4f32 : BaseSIMDThreeSameVectorDot<0b1, 0b0, 0b01, 0b1101, asm, ".4s", ".8h",
6572+
V128, v4f32, v8f16, null_frag>;
6573+
}
6574+
6575+
multiclass SIMDThreeSameVectorFDot<string asm, SDPatternOperator OpNode = null_frag> {
6576+
def v2f32tov4f16 : BaseSIMDThreeSameVectorDot<0, 0, 0b10, 0b1111, asm, ".2s", ".4h", V64,
6577+
v2f32, v4f16, OpNode>;
6578+
def v4f32tov8f16 : BaseSIMDThreeSameVectorDot<1, 0, 0b10, 0b1111, asm, ".4s", ".8h", V128,
6579+
v4f32, v8f16, OpNode>;
6580+
}
6581+
65516582
// FP8 assembly/disassembly classes
65526583

65536584
//----------------------------------------------------------------------------
@@ -9169,6 +9200,13 @@ multiclass SIMDThreeSameVectorFMLIndex<bit U, bits<4> opc, string asm,
91699200
V128, V128_lo, v4f32, v8f16, VectorIndexH, OpNode>;
91709201
}
91719202

9203+
multiclass SIMDThreeSameVectorFDOTIndex<string asm> {
9204+
def v4f16tov2f32 : BaseSIMDThreeSameVectorIndexS<0b0, 0b0, 0b01, 0b1001, asm, ".2s", ".4h", ".2h",
9205+
V64, v2f32, v4f16, VectorIndexS, null_frag>;
9206+
def v8f16tov4f32 : BaseSIMDThreeSameVectorIndexS<0b1, 0b0, 0b01, 0b1001, asm, ".4s", ".8h",".2h",
9207+
V128, v4f32, v8f16, VectorIndexS, null_frag>;
9208+
}
9209+
91729210
//----------------------------------------------------------------------------
91739211
// FP8 Advanced SIMD vector x indexed element
91749212
multiclass SIMD_FP8_Dot2_Index<string asm, SDPatternOperator op> {

‎llvm/lib/Target/AArch64/AArch64InstrInfo.td‎

Lines changed: 16 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -256,6 +256,10 @@ def HasSVE2p3 : Predicate<"Subtarget->hasSVE2p3()">,
256256
AssemblerPredicateWithAll<(all_of FeatureSVE2p3), "sve2p3">;
257257
def HasSME2p3 : Predicate<"Subtarget->hasSME2p3()">,
258258
AssemblerPredicateWithAll<(all_of FeatureSME2p3), "sme2p3">;
259+
def HasF16F32DOT : Predicate<"Subtarget->hasF16F32DOT()">,
260+
AssemblerPredicateWithAll<(all_of FeatureF16F32DOT), "f16f32dot">;
261+
def HasF16F32MM : Predicate<"Subtarget->hasF16F32MM()">,
262+
AssemblerPredicateWithAll<(all_of FeatureF16F32MM), "f16f32mm">;
259263

260264
// A subset of SVE(2) instructions are legal in Streaming SVE execution mode,
261265
// they should be enabled if either has been specified.
@@ -11281,8 +11285,19 @@ let Predicates = [HasLSFE] in {
1128111285
def STBFMINNML : BaseAtomicFPStore<FPR16, 0b00, 0b1, 0b111, "stbfminnml">;
1128211286
}
1128311287

11288+
let Predicates = [HasF16F32DOT] in {
11289+
defm FDOT :SIMDThreeSameVectorFDot<"fdot">;
11290+
defm FDOTlane: SIMDThreeSameVectorFDOTIndex<"fdot">;
11291+
}
11292+
11293+
let Predicates = [HasF16MM] in
11294+
defm FMMLA : SIMDThreeSameVectorFMLA<"fmmla">;
11295+
11296+
let Predicates = [HasF16F32MM] in
11297+
defm FMMLA : SIMDThreeSameVectorFMLAWiden<"fmmla">;
11298+
1128411299
let Uses = [FPMR, FPCR] in
11285-
defm FMMLA : SIMDThreeSameVectorFP8MatrixMul<"fmmla">;
11300+
defm FMMLA : SIMDThreeSameVectorFP8MatrixMul<"fmmla">;
1128611301

1128711302
//===----------------------------------------------------------------------===//
1128811303
// Contention Management Hints (FEAT_CMH)

‎llvm/lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp‎

Lines changed: 2 additions & 0 deletions
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@@ -3894,6 +3894,8 @@ static const struct Extension {
38943894
{"sve2p3", {AArch64::FeatureSVE2p3}},
38953895
{"sve-b16mm", {AArch64::FeatureSVE_B16MM}},
38963896
{"f16mm", {AArch64::FeatureF16MM}},
3897+
{"f16f32dot", {AArch64::FeatureF16F32DOT}},
3898+
{"f16f32mm", {AArch64::FeatureF16F32MM}},
38973899
};
38983900

38993901
static void setRequiredFeatureString(FeatureBitset FBS, std::string &Str) {

‎llvm/test/MC/AArch64/FP8/fmmla-diagnostics.s‎

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -16,7 +16,7 @@ fmmla v0.4s, v1.4s, v2.4s
1616
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
1717

1818
fmmla v0.8h, v1.8h, v2.8h
19-
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
19+
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction requires: f16mm
2020
// CHECK-NEXT: fmmla v0.8h, v1.8h, v2.8h
2121
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
2222

‎llvm/test/MC/AArch64/neon-fdot-diagnostics.s‎

Lines changed: 59 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,59 @@
1+
// RUN: not llvm-mc -triple=aarch64 -mattr=f16f32dot 2>&1 < %s| FileCheck %s
2+
3+
// --------------------------------------------------------------------------//
4+
// Invalid operand
5+
6+
fdot v0.2s, v0.4b, v0.4b
7+
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
8+
// CHECK-NEXT: fdot v0.2s, v0.4b, v0.4b
9+
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
10+
11+
fdot v0.2b, v0.4b, v0.4b
12+
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
13+
// CHECK-NEXT: fdot v0.2b, v0.4b, v0.4b
14+
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
15+
16+
fdot v0.2s, v0.4s, v0.4s
17+
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
18+
// CHECK-NEXT: fdot v0.2s, v0.4s, v0.4s
19+
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
20+
21+
fdot v0.2h, v0.4h, v0.4h
22+
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
23+
// CHECK-NEXT: fdot v0.2h, v0.4h, v0.4h
24+
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
25+
26+
// fdot indexed
27+
28+
fdot v0.2s, v0.4b, v0.4b[0]
29+
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
30+
// CHECK-NEXT: fdot v0.2s, v0.4b, v0.4b
31+
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
32+
33+
fdot v0.2b, v0.4b, v0.4b[0]
34+
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
35+
// CHECK-NEXT: fdot v0.2b, v0.4b, v0.4b
36+
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
37+
38+
fdot v0.2s, v0.4s, v0.4s[0]
39+
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
40+
// CHECK-NEXT: fdot v0.2s, v0.4s, v0.4s
41+
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
42+
43+
fdot v0.2h, v0.4h, v0.4h[0]
44+
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
45+
// CHECK-NEXT: fdot v0.2h, v0.4h, v0.4h
46+
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
47+
48+
// --------------------------------------------------------------------------//
49+
// Invalid immediate range
50+
51+
fdot v0.2s, v0.4h, v0.2h[-1]
52+
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: vector lane must be an integer in range [0, 3].
53+
// CHECK-NEXT: fdot v0.2s, v0.4h, v0.2h[-1]
54+
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
55+
56+
fdot v0.2s, v0.4h, v0.2h[4]
57+
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: vector lane must be an integer in range [0, 3].
58+
// CHECK-NEXT: fdot v0.2s, v0.4h, v0.2h[4]
59+
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:

‎llvm/test/MC/AArch64/neon-fdot.s‎

Lines changed: 147 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,147 @@
1+
// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+f16f32dot < %s \
2+
// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
3+
// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
4+
// RUN: | FileCheck %s --check-prefix=CHECK-ERROR
5+
// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+f16f32dot < %s \
6+
// RUN: | llvm-objdump -d --mattr=+f16f32dot --no-print-imm-hex - | FileCheck %s --check-prefix=CHECK-INST
7+
// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+f16f32dot < %s \
8+
// RUN: | llvm-objdump -d --mattr=-f16f32dot --no-print-imm-hex - | FileCheck %s --check-prefix=CHECK-UNKNOWN
9+
// Disassemble encoding and check the re-encoding (-show-encoding) matches.
10+
// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+f16f32dot < %s \
11+
// RUN: | sed '/.text/d' | sed 's/.*encoding: //g' \
12+
// RUN: | llvm-mc -triple=aarch64 -mattr=+f16f32dot -disassemble -show-encoding \
13+
// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
14+
15+
fdot v0.2s, v0.4h, v0.4h
16+
// CHECK-INST: fdot v0.2s, v0.4h, v0.4h
17+
// CHECK-ENCODING: encoding: [0x00,0xfc,0x80,0x0e]
18+
// CHECK-ERROR: instruction requires: f16f32dot
19+
// CHECK-UNKNOWN: 0e80fc00 <unknown>
20+
21+
fdot v10.2s, v10.4h, v10.4h
22+
// CHECK-INST: fdot v10.2s, v10.4h, v10.4h
23+
// CHECK-ENCODING: encoding: [0x4a,0xfd,0x8a,0x0e]
24+
// CHECK-ERROR: instruction requires: f16f32dot
25+
// CHECK-UNKNOWN: 0e8afd4a <unknown>
26+
27+
fdot v31.2s, v31.4h, v31.4h
28+
// CHECK-INST: fdot v31.2s, v31.4h, v31.4h
29+
// CHECK-ENCODING: encoding: [0xff,0xff,0x9f,0x0e]
30+
// CHECK-ERROR: instruction requires: f16f32dot
31+
// CHECK-UNKNOWN: 0e9fffff <unknown>
32+
33+
fdot v0.4s, v0.8h, v0.8h
34+
// CHECK-INST: fdot v0.4s, v0.8h, v0.8h
35+
// CHECK-ENCODING: encoding: [0x00,0xfc,0x80,0x4e]
36+
// CHECK-ERROR: instruction requires: f16f32dot
37+
// CHECK-UNKNOWN: 4e80fc00 <unknown>
38+
39+
fdot v10.4s, v10.8h, v10.8h
40+
// CHECK-INST: fdot v10.4s, v10.8h, v10.8h
41+
// CHECK-ENCODING: encoding: [0x4a,0xfd,0x8a,0x4e]
42+
// CHECK-ERROR: instruction requires: f16f32dot
43+
// CHECK-UNKNOWN: 4e8afd4a <unknown>
44+
45+
fdot v31.4s, v31.8h, v31.8h
46+
// CHECK-INST: fdot v31.4s, v31.8h, v31.8h
47+
// CHECK-ENCODING: encoding: [0xff,0xff,0x9f,0x4e]
48+
// CHECK-ERROR: instruction requires: f16f32dot
49+
// CHECK-UNKNOWN: 4e9fffff <unknown>
50+
51+
// fdot indexed
52+
53+
fdot v0.2s, v0.4h, v0.2h[0]
54+
// CHECK-INST: fdot v0.2s, v0.4h, v0.2h[0]
55+
// CHECK-ENCODING: encoding: [0x00,0x90,0x40,0x0f]
56+
// CHECK-ERROR: instruction requires: f16f32dot
57+
// CHECK-UNKNOWN: 0f409000 <unknown>
58+
59+
fdot v10.2s, v0.4h, v0.2h[0]
60+
// CHECK-INST: fdot v10.2s, v0.4h, v0.2h[0]
61+
// CHECK-ENCODING: encoding: [0x0a,0x90,0x40,0x0f]
62+
// CHECK-ERROR: instruction requires: f16f32dot
63+
// CHECK-UNKNOWN: 0f40900a <unknown>
64+
65+
fdot v21.2s, v0.4h, v0.2h[0]
66+
// CHECK-INST: fdot v21.2s, v0.4h, v0.2h[0]
67+
// CHECK-ENCODING: encoding: [0x15,0x90,0x40,0x0f]
68+
// CHECK-ERROR: instruction requires: f16f32dot
69+
// CHECK-UNKNOWN: 0f409015 <unknown>
70+
71+
fdot v31.2s, v0.4h, v0.2h[0]
72+
// CHECK-INST: fdot v31.2s, v0.4h, v0.2h[0]
73+
// CHECK-ENCODING: encoding: [0x1f,0x90,0x40,0x0f]
74+
// CHECK-ERROR: instruction requires: f16f32dot
75+
// CHECK-UNKNOWN: 0f40901f <unknown>
76+
77+
fdot v0.2s, v10.4h, v0.2h[0]
78+
// CHECK-INST: fdot v0.2s, v10.4h, v0.2h[0]
79+
// CHECK-ENCODING: encoding: [0x40,0x91,0x40,0x0f]
80+
// CHECK-ERROR: instruction requires: f16f32dot
81+
// CHECK-UNKNOWN: 0f409140 <unknown>
82+
83+
fdot v10.2s, v10.4h, v0.2h[0]
84+
// CHECK-INST: fdot v10.2s, v10.4h, v0.2h[0]
85+
// CHECK-ENCODING: encoding: [0x4a,0x91,0x40,0x0f]
86+
// CHECK-ERROR: instruction requires: f16f32dot
87+
// CHECK-UNKNOWN: 0f40914a <unknown>
88+
89+
fdot v21.2s, v10.4h, v0.2h[0]
90+
// CHECK-INST: fdot v21.2s, v10.4h, v0.2h[0]
91+
// CHECK-ENCODING: encoding: [0x55,0x91,0x40,0x0f]
92+
// CHECK-ERROR: instruction requires: f16f32dot
93+
// CHECK-UNKNOWN: 0f409155 <unknown>
94+
95+
fdot v31.2s, v10.4h, v0.2h[0]
96+
// CHECK-INST: fdot v31.2s, v10.4h, v0.2h[0]
97+
// CHECK-ENCODING: encoding: [0x5f,0x91,0x40,0x0f]
98+
// CHECK-ERROR: instruction requires: f16f32dot
99+
// CHECK-UNKNOWN: 0f40915f <unknown>
100+
101+
fdot v0.4s, v21.8h, v31.2h[3]
102+
// CHECK-INST: fdot v0.4s, v21.8h, v31.2h[3]
103+
// CHECK-ENCODING: encoding: [0xa0,0x9a,0x7f,0x4f]
104+
// CHECK-ERROR: instruction requires: f16f32dot
105+
// CHECK-UNKNOWN: 4f7f9aa0 <unknown>
106+
107+
fdot v10.4s, v21.8h, v31.2h[3]
108+
// CHECK-INST: fdot v10.4s, v21.8h, v31.2h[3]
109+
// CHECK-ENCODING: encoding: [0xaa,0x9a,0x7f,0x4f]
110+
// CHECK-ERROR: instruction requires: f16f32dot
111+
// CHECK-UNKNOWN: 4f7f9aaa <unknown>
112+
113+
fdot v21.4s, v21.8h, v31.2h[3]
114+
// CHECK-INST: fdot v21.4s, v21.8h, v31.2h[3]
115+
// CHECK-ENCODING: encoding: [0xb5,0x9a,0x7f,0x4f]
116+
// CHECK-ERROR: instruction requires: f16f32dot
117+
// CHECK-UNKNOWN: 4f7f9ab5 <unknown>
118+
119+
fdot v31.4s, v21.8h, v31.2h[3]
120+
// CHECK-INST: fdot v31.4s, v21.8h, v31.2h[3]
121+
// CHECK-ENCODING: encoding: [0xbf,0x9a,0x7f,0x4f]
122+
// CHECK-ERROR: instruction requires: f16f32dot
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// CHECK-UNKNOWN: 4f7f9abf <unknown>
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fdot v0.4s, v31.8h, v31.2h[3]
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// CHECK-INST: fdot v0.4s, v31.8h, v31.2h[3]
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// CHECK-ENCODING: encoding: [0xe0,0x9b,0x7f,0x4f]
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// CHECK-ERROR: instruction requires: f16f32dot
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// CHECK-UNKNOWN: 4f7f9be0 <unknown>
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fdot v10.4s, v31.8h, v31.2h[3]
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// CHECK-INST: fdot v10.4s, v31.8h, v31.2h[3]
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// CHECK-ENCODING: encoding: [0xea,0x9b,0x7f,0x4f]
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// CHECK-ERROR: instruction requires: f16f32dot
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// CHECK-UNKNOWN: 4f7f9bea <unknown>
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fdot v21.4s, v31.8h, v31.2h[3]
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// CHECK-INST: fdot v21.4s, v31.8h, v31.2h[3]
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// CHECK-ENCODING: encoding: [0xf5,0x9b,0x7f,0x4f]
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// CHECK-ERROR: instruction requires: f16f32dot
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// CHECK-UNKNOWN: 4f7f9bf5 <unknown>
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fdot v31.4s, v31.8h, v31.2h[3]
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// CHECK-INST: fdot v31.4s, v31.8h, v31.2h[3]
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// CHECK-ENCODING: encoding: [0xff,0x9b,0x7f,0x4f]
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// CHECK-ERROR: instruction requires: f16f32dot
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// CHECK-UNKNOWN: 4f7f9bff <unknown>

‎llvm/test/MC/AArch64/neon-fmmla-HtoS-diagnostics.s‎

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// RUN: not llvm-mc -triple=aarch64 -mattr=+f16f32mm 2>&1 < %s| FileCheck %s
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// --------------------------------------------------------------------------//
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// Invalid operand/vector
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fmmla v0.4b, v0.8b, v0.8b
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// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
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// CHECK-NEXT: fmmla v0.4b, v0.8b, v0.8b
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// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
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fmmla v0.4h, v0.8h, v0.8h
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// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
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// CHECK-NEXT: fmmla v0.4h, v0.8h, v0.8h
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// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
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fmmla v0.4s, v0.8s, v0.8s
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// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid vector kind qualifier
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// CHECK-NEXT: fmmla v0.4s, v0.8s, v0.8s
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// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
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fmmla v0.4d, v0.8d, v0.8d
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// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid vector kind qualifier
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// CHECK-NEXT: fmmla v0.4d, v0.8d, v0.8d
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// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:

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