Fixups

Author: MacDue

llvm/lib/CodeGen/ValueTypes.cpp

@@ -224,7 +224,7 @@ Type *EVT::getTypeForEVT(LLVMContext &Context) const {
   case MVT::aarch64svcount:
     return TargetExtType::get(Context, "aarch64.svcount");
   case MVT::aarch64mfp8:
-    return VectorType::get(IntegerType::get(Context, 8), ElementCount::getFixed(1));
+    return FixedVectorType::get(IntegerType::get(Context, 8), 1);
   case MVT::x86amx:  return Type::getX86_AMXTy(Context);
   case MVT::i64x8:   return IntegerType::get(Context, 512);
   case MVT::amdgpuBufferFatPointer:  return IntegerType::get(Context, 160);

llvm/lib/Target/AArch64/AArch64ISelLowering.cpp

@@ -24036,13 +24036,12 @@ static SDValue performSTORECombine(SDNode *N,
     if ((!ExtCst || !ExtCst->isZero()) && !Value.hasOneUse())
       return SDValue();
 
+    // These can lower to st1, which is preferable if we're unlikely to fold the
+    // addressing into the store.
     if (Subtarget->isNeonAvailable() && ElemVT == MemVT &&
         (VectorVT.is64BitVector() || VectorVT.is128BitVector()) && ExtCst &&
-        !ExtCst->isZero() && ST->getBasePtr().getOpcode() != ISD::ADD) {
-      // These can lower to st1, which is preferable if we're unlikely to fold
-      // the addressing into the store.
+        !ExtCst->isZero() && ST->getBasePtr().getOpcode() != ISD::ADD)
       return SDValue();
-    }
 
     if (MemVT == MVT::i64 || MemVT == MVT::i32) {
       // Heuristic: If there are other users of w/x integer scalars extracted
@@ -24066,10 +24065,11 @@ static SDValue performSTORECombine(SDNode *N,
                                 Value.getValueType(), Vector, ExtIdx);
       // FIXME: Using a fixed-size vector for the insertion should not be
       // necessary, but SVE ISEL is missing some folds to avoid fmovs.
-      SDValue Zero = DAG.getConstant(0, DL, MVT::i64);
+      SDValue Zero = DAG.getVectorIdxConstant(0, DL);
       EVT InsertVectorVT = EVT::getVectorVT(
           *DAG.getContext(), ElemVT,
-          VectorVT.getVectorElementCount().getKnownMinValue(), false);
+          ElementCount::getFixed(
+              VectorVT.getVectorElementCount().getKnownMinValue()));
       ExtVector = DAG.getNode(ISD::INSERT_VECTOR_ELT, DL, InsertVectorVT,
                               DAG.getUNDEF(InsertVectorVT), Ext, Zero);
     }

llvm/lib/Target/AArch64/AArch64InstrInfo.td

@@ -4604,8 +4604,8 @@ def : Pat<(truncstorei8 GPR64:$Rt, (am_unscaled8 GPR64sp:$Rn, simm9:$offset)),
 // aarch64mfp8 (bsub) stores
 def : Pat<(store aarch64mfp8:$Rt, (am_unscaled8 GPR64sp:$Rn, simm9:$offset)),
           (STURBi FPR8:$Rt, GPR64sp:$Rn, simm9:$offset)>;
-def : Pat<(store aarch64mfp8:$Rt, (am_indexed8 GPR64sp:$Rn, uimm12s4:$offset)),
-          (STRBui FPR8:$Rt, GPR64sp:$Rn, uimm12s4:$offset)>;
+def : Pat<(store aarch64mfp8:$Rt, (am_indexed8 GPR64sp:$Rn, uimm12s1:$offset)),
+          (STRBui FPR8:$Rt, GPR64sp:$Rn, uimm12s1:$offset)>;
 
 // Match stores from lane 0 to the appropriate subreg's store.
 multiclass VecStoreULane0Pat<SDPatternOperator StoreOp,