@@ -79,11 +79,6 @@ static bool isVectorRegClass(Register R, const MachineRegisterInfo *MRI) {
7979
8080// / Represents the EMUL and EEW of a MachineOperand.
8181struct OperandInfo {
82- enum class State {
83- Unknown,
84- Known,
85- } S;
86-
8782 // Represent as 1,2,4,8, ... and fractional indicator. This is because
8883 // EMUL can take on values that don't map to RISCVII::VLMUL values exactly.
8984 // For example, a mask operand can have an EMUL less than MF8.
@@ -92,41 +87,33 @@ struct OperandInfo {
9287 unsigned Log2EEW;
9388
9489 OperandInfo (RISCVII::VLMUL EMUL, unsigned Log2EEW)
95- : S(State::Known), EMUL(RISCVVType::decodeVLMUL(EMUL)), Log2EEW(Log2EEW) {
90+ : EMUL(RISCVVType::decodeVLMUL(EMUL)), Log2EEW(Log2EEW) {
9691 }
9792
9893 OperandInfo (std::pair<unsigned , bool > EMUL, unsigned Log2EEW)
99- : S(State::Known), EMUL(EMUL), Log2EEW(Log2EEW) {}
100-
101- OperandInfo (unsigned Log2EEW) : S(State::Known), Log2EEW(Log2EEW) {}
94+ : EMUL(EMUL), Log2EEW(Log2EEW) {}
10295
103- OperandInfo () : S(State::Unknown ) {}
96+ OperandInfo (unsigned Log2EEW ) : Log2EEW(Log2EEW ) {}
10497
105- bool isUnknown () const { return S == State::Unknown; }
106- bool isKnown () const { return S == State::Known; }
98+ OperandInfo () = delete ;
10799
108100 static bool EMULAndEEWAreEqual (const OperandInfo &A, const OperandInfo &B) {
109- assert (A.isKnown () && B.isKnown () && " Both operands must be known" );
110-
111101 return A.Log2EEW == B.Log2EEW && A.EMUL ->first == B.EMUL ->first &&
112102 A.EMUL ->second == B.EMUL ->second ;
113103 }
114104
115105 static bool EEWAreEqual (const OperandInfo &A, const OperandInfo &B) {
116- assert (A.isKnown () && B.isKnown () && " Both operands must be known" );
117106 return A.Log2EEW == B.Log2EEW ;
118107 }
119108
120109 void print (raw_ostream &OS) const {
121- if (isUnknown ()) {
122- OS << " Unknown" ;
123- return ;
124- }
125- assert (EMUL && " Expected EMUL to have value" );
126- OS << " EMUL: m" ;
127- if (EMUL->second )
128- OS << " f" ;
129- OS << EMUL->first ;
110+ if (EMUL) {
111+ OS << " EMUL: m" ;
112+ if (EMUL->second )
113+ OS << " f" ;
114+ OS << EMUL->first ;
115+ } else
116+ OS << " EMUL: unknown\n " ;
130117 OS << " , EEW: " << (1 << Log2EEW);
131118 }
132119};
@@ -137,6 +124,17 @@ static raw_ostream &operator<<(raw_ostream &OS, const OperandInfo &OI) {
137124 return OS;
138125}
139126
127+ LLVM_ATTRIBUTE_UNUSED
128+ static raw_ostream &operator <<(raw_ostream &OS,
129+ const std::optional<OperandInfo> &OI) {
130+ if (OI)
131+ OI->print (OS);
132+ else
133+ OS << " nullopt" ;
134+ return OS;
135+ }
136+
137+
140138namespace llvm {
141139namespace RISCVVType {
142140// / Return EMUL = (EEW / SEW) * LMUL where EEW comes from Log2EEW and LMUL and
@@ -715,20 +713,21 @@ getOperandLog2EEW(const MachineOperand &MO, const MachineRegisterInfo *MRI) {
715713 }
716714
717715 default :
718- return {} ;
716+ return std:: nullopt ;
719717 }
720718}
721719
722- static OperandInfo getOperandInfo (const MachineOperand &MO,
723- const MachineRegisterInfo *MRI) {
720+ static std::optional<OperandInfo>
721+ getOperandInfo (const MachineOperand &MO,
722+ const MachineRegisterInfo *MRI) {
724723 const MachineInstr &MI = *MO.getParent ();
725724 const RISCVVPseudosTable::PseudoInfo *RVV =
726725 RISCVVPseudosTable::getPseudoInfo (MI.getOpcode ());
727726 assert (RVV && " Could not find MI in PseudoTable" );
728727
729728 std::optional<unsigned > Log2EEW = getOperandLog2EEW (MO, MRI);
730729 if (!Log2EEW)
731- return {} ;
730+ return std:: nullopt ;
732731
733732 switch (RVV->BaseInstr ) {
734733 // Vector Reduction Operations
@@ -1185,9 +1184,10 @@ std::optional<MachineOperand> RISCVVLOptimizer::checkUsers(MachineInstr &MI) {
11851184 return std::nullopt ;
11861185 }
11871186
1188- OperandInfo ConsumerInfo = getOperandInfo (UserOp, MRI);
1189- OperandInfo ProducerInfo = getOperandInfo (MI.getOperand (0 ), MRI);
1190- if (ConsumerInfo.isUnknown () || ProducerInfo.isUnknown ()) {
1187+ std::optional<OperandInfo> ConsumerInfo = getOperandInfo (UserOp, MRI);
1188+ std::optional<OperandInfo> ProducerInfo =
1189+ getOperandInfo (MI.getOperand (0 ), MRI);
1190+ if (!ConsumerInfo || !ProducerInfo) {
11911191 LLVM_DEBUG (dbgs () << " Abort due to unknown operand information.\n " );
11921192 LLVM_DEBUG (dbgs () << " ConsumerInfo is: " << ConsumerInfo << " \n " );
11931193 LLVM_DEBUG (dbgs () << " ProducerInfo is: " << ProducerInfo << " \n " );
@@ -1198,9 +1198,9 @@ std::optional<MachineOperand> RISCVVLOptimizer::checkUsers(MachineInstr &MI) {
11981198 // compatible. Otherwise, the EMUL *and* EEW must be compatible.
11991199 bool IsVectorOpUsedAsScalarOp = isVectorOpUsedAsScalarOp (UserOp);
12001200 if ((IsVectorOpUsedAsScalarOp &&
1201- !OperandInfo::EEWAreEqual (ConsumerInfo, ProducerInfo)) ||
1201+ !OperandInfo::EEWAreEqual (* ConsumerInfo, * ProducerInfo)) ||
12021202 (!IsVectorOpUsedAsScalarOp &&
1203- !OperandInfo::EMULAndEEWAreEqual (ConsumerInfo, ProducerInfo))) {
1203+ !OperandInfo::EMULAndEEWAreEqual (* ConsumerInfo, * ProducerInfo))) {
12041204 LLVM_DEBUG (
12051205 dbgs ()
12061206 << " Abort due to incompatible information for EMUL or EEW.\n " );
0 commit comments