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[PowerPC] Implement paddis
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12 files changed

+119
-2
lines changed

12 files changed

+119
-2
lines changed

‎llvm/lib/Target/PowerPC/AsmParser/PPCAsmParser.cpp‎

Lines changed: 4 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -365,6 +365,10 @@ struct PPCOperand : public MCParsedAsmOperand {
365365
bool isS16ImmX4() const { return isExtImm<16>(/*Signed*/ true, 4); }
366366
bool isS16ImmX16() const { return isExtImm<16>(/*Signed*/ true, 16); }
367367
bool isS17Imm() const { return isExtImm<17>(/*Signed*/ true, 1); }
368+
bool isS32Imm() const {
369+
// TODO: Is ContextImmediate needed?
370+
return Kind == Expression || isSImm<32>();
371+
}
368372
bool isS34Imm() const {
369373
// Once the PC-Rel ABI is finalized, evaluate whether a 34-bit
370374
// ContextImmediate is needed.

‎llvm/lib/Target/PowerPC/MCTargetDesc/PPCAsmBackend.cpp‎

Lines changed: 9 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -47,6 +47,9 @@ static uint64_t adjustFixupValue(unsigned Kind, uint64_t Value) {
4747
case PPC::fixup_ppc_half16ds:
4848
case PPC::fixup_ppc_half16dq:
4949
return Value & 0xfffc;
50+
case PPC::fixup_ppc_pcrel32:
51+
case PPC::fixup_ppc_imm32:
52+
return Value & 0xffffffff;
5053
case PPC::fixup_ppc_pcrel34:
5154
case PPC::fixup_ppc_imm34:
5255
return Value & 0x3ffffffff;
@@ -71,6 +74,8 @@ static unsigned getFixupKindNumBytes(unsigned Kind) {
7174
case PPC::fixup_ppc_br24abs:
7275
case PPC::fixup_ppc_br24_notoc:
7376
return 4;
77+
case PPC::fixup_ppc_pcrel32:
78+
case PPC::fixup_ppc_imm32:
7479
case PPC::fixup_ppc_pcrel34:
7580
case PPC::fixup_ppc_imm34:
7681
case FK_Data_8:
@@ -154,6 +159,8 @@ MCFixupKindInfo PPCAsmBackend::getFixupKindInfo(MCFixupKind Kind) const {
154159
{"fixup_ppc_brcond14abs", 16, 14, 0},
155160
{"fixup_ppc_half16", 0, 16, 0},
156161
{"fixup_ppc_half16ds", 0, 14, 0},
162+
{"fixup_ppc_pcrel32", 0, 32, 0},
163+
{"fixup_ppc_imm32", 0, 32, 0},
157164
{"fixup_ppc_pcrel34", 0, 34, 0},
158165
{"fixup_ppc_imm34", 0, 34, 0},
159166
{"fixup_ppc_nofixup", 0, 0, 0}};
@@ -166,6 +173,8 @@ MCFixupKindInfo PPCAsmBackend::getFixupKindInfo(MCFixupKind Kind) const {
166173
{"fixup_ppc_brcond14abs", 2, 14, 0},
167174
{"fixup_ppc_half16", 0, 16, 0},
168175
{"fixup_ppc_half16ds", 2, 14, 0},
176+
{"fixup_ppc_pcrel32", 0, 32, 0},
177+
{"fixup_ppc_imm32", 0, 32, 0},
169178
{"fixup_ppc_pcrel34", 0, 34, 0},
170179
{"fixup_ppc_imm34", 0, 34, 0},
171180
{"fixup_ppc_nofixup", 0, 0, 0}};

‎llvm/lib/Target/PowerPC/MCTargetDesc/PPCFixupKinds.h‎

Lines changed: 6 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -40,6 +40,12 @@ enum Fixups {
4040
/// instrs like 'std'.
4141
fixup_ppc_half16ds,
4242

43+
// A 32-bit fixup corresponding to PC-relative paddis.
44+
fixup_ppc_pcrel32,
45+
46+
// A 32-bit fixup corresponding to Non-PC-relative paddis.
47+
fixup_ppc_imm32,
48+
4349
// A 34-bit fixup corresponding to PC-relative paddi.
4450
fixup_ppc_pcrel34,
4551

‎llvm/lib/Target/PowerPC/MCTargetDesc/PPCInstPrinter.cpp‎

Lines changed: 12 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -430,6 +430,18 @@ void PPCInstPrinter::printS16ImmOperand(const MCInst *MI, unsigned OpNo,
430430
printOperand(MI, OpNo, STI, O);
431431
}
432432

433+
void PPCInstPrinter::printS32ImmOperand(const MCInst *MI, unsigned OpNo,
434+
const MCSubtargetInfo &STI,
435+
raw_ostream &O) {
436+
if (MI->getOperand(OpNo).isImm()) {
437+
long long Value = MI->getOperand(OpNo).getImm();
438+
assert(isInt<32>(Value) && "Invalid s32imm argument!");
439+
O << (long long)Value;
440+
}
441+
else
442+
printOperand(MI, OpNo, STI, O);
443+
}
444+
433445
void PPCInstPrinter::printS34ImmOperand(const MCInst *MI, unsigned OpNo,
434446
const MCSubtargetInfo &STI,
435447
raw_ostream &O) {

‎llvm/lib/Target/PowerPC/MCTargetDesc/PPCInstPrinter.h‎

Lines changed: 2 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -80,6 +80,8 @@ class PPCInstPrinter : public MCInstPrinter {
8080
const MCSubtargetInfo &STI, raw_ostream &O);
8181
void printS16ImmOperand(const MCInst *MI, unsigned OpNo,
8282
const MCSubtargetInfo &STI, raw_ostream &O);
83+
void printS32ImmOperand(const MCInst *MI, unsigned OpNo,
84+
const MCSubtargetInfo &STI, raw_ostream &O);
8385
void printS34ImmOperand(const MCInst *MI, unsigned OpNo,
8486
const MCSubtargetInfo &STI, raw_ostream &O);
8587
void printU16ImmOperand(const MCInst *MI, unsigned OpNo,

‎llvm/lib/Target/PowerPC/MCTargetDesc/PPCMCCodeEmitter.cpp‎

Lines changed: 1 addition & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -46,6 +46,7 @@ static void addFixup(SmallVectorImpl<MCFixup> &Fixups, uint32_t Offset,
4646
case PPC::fixup_ppc_br24_notoc:
4747
case PPC::fixup_ppc_brcond14:
4848
case PPC::fixup_ppc_pcrel34:
49+
case PPC::fixup_ppc_pcrel32:
4950
PCRel = true;
5051
}
5152
Fixups.push_back(MCFixup::create(Offset, Value, Kind, PCRel));

‎llvm/lib/Target/PowerPC/PPCInstrFuture.td‎

Lines changed: 44 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -312,9 +312,41 @@ class 8RR_XX4Form_XTABC6_P<bits<6> opcode, dag OOL, dag IOL, string asmstr,
312312
let Inst{63} = XT{5};
313313
}
314314

315+
class MLS_DForm_R_SI32_RTA5<bits<6> opcode, dag OOL, dag IOL, string asmstr,
316+
InstrItinClass itin, list<dag> pattern>
317+
: PI<1, opcode, OOL, IOL, asmstr, itin> {
318+
bits<5> RT;
319+
bits<5> RA;
320+
bits<32> SI;
321+
322+
let Pattern = pattern;
323+
324+
// The prefix.
325+
let Inst{6...7} = 2;
326+
let Inst{8} = 0;
327+
let Inst{11} = PCRel;
328+
let Inst{16...31} = SI{31...16};
329+
330+
// The instruction.
331+
let Inst{38...42} = RT;
332+
let Inst{43...47} = RA;
333+
let Inst{48...63} = SI{15...0};
334+
}
335+
336+
multiclass MLS_DForm_R_SI32_RTA5_p<bits<6> opcode, dag OOL, dag IOL,
337+
dag PCRel_IOL, string asmstr,
338+
InstrItinClass itin> {
339+
def NAME : MLS_DForm_R_SI32_RTA5<opcode, OOL, IOL, !strconcat(asmstr, ", 0"),
340+
itin, []>;
341+
def pc : MLS_DForm_R_SI32_RTA5<opcode, OOL, PCRel_IOL,
342+
!strconcat(asmstr, ", 1"), itin, []>,
343+
isPCRel;
344+
}
345+
315346
//-------------------------- Instruction definitions -------------------------//
316347
// Predicate combinations available:
317348
// [IsISAFuture]
349+
// [IsISAFuture, PrefixInstrs]
318350
// [HasVSX, IsISAFuture]
319351
// [HasVSX, PrefixInstrs, IsISAFuture]
320352

@@ -346,6 +378,18 @@ let Predicates = [IsISAFuture] in {
346378
}
347379
}
348380

381+
let Predicates = [IsISAFuture, PrefixInstrs] in {
382+
defm PADDIS : MLS_DForm_R_SI32_RTA5_p<15, (outs gprc:$RT),
383+
(ins gprc_nor0:$RA, s32imm:$SI),
384+
(ins immZero:$RA, s32imm_pcrel:$SI),
385+
"paddis $RT, $RA, $SI", IIC_LdStLFD>;
386+
let Interpretation64Bit = 1, isCodeGenOnly = 1 in
387+
defm PADDIS8 : MLS_DForm_R_SI32_RTA5_p<15, (outs g8rc:$RT),
388+
(ins g8rc_nox0:$RA, s32imm:$SI),
389+
(ins immZero:$RA, s32imm_pcrel:$SI),
390+
"paddis $RT, $RA, $SI", IIC_LdStLFD>;
391+
}
392+
349393
let Predicates = [HasVSX, IsISAFuture] in {
350394
let mayLoad = 1 in {
351395
def LXVRL : XX1Form_memOp<31, 525, (outs vsrc:$XT),

‎llvm/lib/Target/PowerPC/PPCRegisterInfo.td‎

Lines changed: 19 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -808,6 +808,25 @@ def s17imm64 : Operand<i64> {
808808
let DecoderMethod = "decodeSImmOperand<16>";
809809
let OperandType = "OPERAND_IMMEDIATE";
810810
}
811+
def PPCS32ImmAsmOperand : AsmOperandClass {
812+
let Name = "S32Imm";
813+
let PredicateMethod = "isS32Imm";
814+
let RenderMethod = "addImmOperands";
815+
}
816+
def s32imm : Operand<i64> {
817+
let PrintMethod = "printS32ImmOperand";
818+
let EncoderMethod = "getImmEncoding<PPC::fixup_ppc_imm32>";
819+
let ParserMatchClass = PPCS32ImmAsmOperand;
820+
let DecoderMethod = "decodeSImmOperand<32>";
821+
let OperandType = "OPERAND_IMMEDIATE";
822+
}
823+
def s32imm_pcrel : Operand<i64> {
824+
let PrintMethod = "printS32ImmOperand";
825+
let EncoderMethod = "getImmEncoding<PPC::fixup_ppc_pcrel32>";
826+
let ParserMatchClass = PPCS32ImmAsmOperand;
827+
let DecoderMethod = "decodeSImmOperand<32>";
828+
let OperandType = "OPERAND_IMMEDIATE";
829+
}
811830
def PPCS34ImmAsmOperand : AsmOperandClass {
812831
let Name = "S34Imm";
813832
let PredicateMethod = "isS34Imm";

‎llvm/test/MC/Disassembler/PowerPC/ppc-encoding-ISAFuture.txt‎

Lines changed: 6 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -289,6 +289,12 @@
289289
#CHECK: mtlpl 3, 4
290290
0x7c,0x80,0x1a,0x26
291291

292+
#CHECK: paddis 10, 12, 1000000000, 0
293+
0x06,0x00,0x3b,0x9a,0x3d,0x4c,0xca,0x00
294+
295+
#CHECK: paddis 10, 0, 1000000000, 1
296+
0x06,0x10,0x3b,0x9a,0x3d,0x40,0xca,0x00
297+
292298
#CHECK: xxmulmul 8, 3, 4, 2
293299
0xed,0x03,0x22,0x08
294300

‎llvm/test/MC/Disassembler/PowerPC/ppc64le-encoding-ISAFuture.txt‎

Lines changed: 6 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -283,6 +283,12 @@
283283
#CHECK: mtlpl 3, 4
284284
0x26,0x1a,0x80,0x7c
285285

286+
#CHECK: paddis 10, 12, 1000000000, 0
287+
0x9a,0x3b,0x00,0x06,0x00,0xca,0x4c,0x3d
288+
289+
#CHECK: paddis 10, 0, 1000000000, 1
290+
0x9a,0x3b,0x10,0x06,0x00,0xca,0x40,0x3d
291+
286292
#CHECK: xxmulmul 8, 3, 4, 2
287293
0x08,0x22,0x03,0xed
288294

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