rebasing

Author: fschlimb

llvm/lib/Target/X86/X86FastISel.cpp

@@ -3544,7 +3544,9 @@ bool X86FastISel::fastLowerCall(CallLoweringInfo &CLI) {
 
     MIB = BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, MIMD, TII.get(CallOpc));
     if (NeedLoad)
-      MIB.addReg(Is64Bit ? X86::RIP : 0).addImm(1).addReg(0);
+      MIB.addReg(Is64Bit ? static_cast<unsigned>(X86::RIP) : 0U)
+          .addImm(1)
+          .addReg(0);
     if (Symbol)
       MIB.addSym(Symbol, OpFlags);
     else

llvm/lib/Target/X86/X86ISelLowering.cpp

@@ -29986,14 +29986,9 @@ static SDValue LowerShift(SDValue Op, const X86Subtarget &Subtarget,
           MVT::getVectorVT(NarrowScalarVT, WideNumElts), dl, AmtWideElts);
       AmtWide = DAG.getZExtOrTrunc(AmtWide, dl, WideVT);
       // Perform the actual shift.
-<<<<<<< HEAD
-      unsigned LogicalOpc = Opc == ISD::SRA ? ISD::SRL : Opc;
-      SDValue ShiftedR = DAG.getNode(LogicalOpc, dl, WideVT, RWide, AmtWide);
-=======
       unsigned LogicalOpc =
           Opc == ISD::SRA ? static_cast<unsigned>(ISD::SRL) : Opc;
-      SDValue ShiftedR = DAG.getNode(LogicalOpc, dl, VT16, R16, Amt16);
->>>>>>> ae2283c2c014 (static_cast)
+      SDValue ShiftedR = DAG.getNode(LogicalOpc, dl, WideVT, RWide, AmtWide);
       // Now we need to construct a mask which will "drop" bits that get
       // shifted past the LSB/MSB. For a logical shift left, it will look
       // like:

mlir/lib/Dialect/Linalg/Transforms/Vectorization.cpp

@@ -864,7 +864,7 @@ static uint64_t getTrailingNonUnitLoopDimIdx(LinalgOp linalgOp) {
       "For statically shaped Linalg Ops, only one "
       "non-unit loop dim is expected");
 
-  size_t idx = loopRanges.size() - 1;
+  ssize_t idx = loopRanges.size() - 1;
   for (; idx >= 0; idx--)
     if (loopRanges[idx] != 1)
       break;

mlir/lib/Transforms/Utils/DialectConversion.cpp

@@ -1045,9 +1045,8 @@ UnresolvedMaterializationRewrite::UnresolvedMaterializationRewrite(
     const TypeConverter *converter, MaterializationKind kind, Type originalType)
     : OperationRewrite(Kind::UnresolvedMaterialization, rewriterImpl, op),
       converterAndKind(converter, kind), originalType(originalType) {
-  assert(!originalType ||
-         kind == MaterializationKind::Target &&
-             "original type is valid only for target materializations");
+  assert((!originalType || kind == MaterializationKind::Target) &&
+         "original type is valid only for target materializations");
   rewriterImpl.unresolvedMaterializations[op] = this;
 }
 
@@ -1337,9 +1336,8 @@ Value ConversionPatternRewriterImpl::buildUnresolvedMaterialization(
     MaterializationKind kind, OpBuilder::InsertPoint ip, Location loc,
     ValueRange inputs, Type outputType, Type originalType,
     const TypeConverter *converter) {
-  assert(!originalType ||
-         kind == MaterializationKind::Target &&
-             "original type is valid only for target materializations");
+  assert((!originalType || kind == MaterializationKind::Target) &&
+         "original type is valid only for target materializations");
 
   // Avoid materializing an unnecessary cast.
   if (inputs.size() == 1 && inputs.front().getType() == outputType)