Merge branch 'main' into remove-br-undef-transforms-2

Author: nunoplopes

clang/include/clang/Basic/arm_sve.td

@@ -880,7 +880,9 @@ def SVRSQRTS : SInst<"svrsqrts[_{d}]", "ddd", "hfd", MergeNone, "aarch64_sve_frs
 ////////////////////////////////////////////////////////////////////////////////
 // Floating-point reductions
 
-def SVFADDA   : SInst<"svadda[_{d}]",   "sPsd", "hfd", MergeNone, "aarch64_sve_fadda", [VerifyRuntimeMode]>;
+let SVETargetGuard = "sve", SMETargetGuard = InvalidMode in {
+def SVFADDA   : SInst<"svadda[_{d}]",   "sPsd", "hfd", MergeNone, "aarch64_sve_fadda">;
+}
 def SVFADDV   : SInst<"svaddv[_{d}]",   "sPd",  "hfd", MergeNone, "aarch64_sve_faddv", [VerifyRuntimeMode]>;
 def SVFMAXV   : SInst<"svmaxv[_{d}]",   "sPd",  "hfd", MergeNone, "aarch64_sve_fmaxv", [VerifyRuntimeMode]>;
 def SVFMAXNMV : SInst<"svmaxnmv[_{d}]", "sPd",  "hfd", MergeNone, "aarch64_sve_fmaxnmv", [VerifyRuntimeMode]>;

clang/lib/CodeGen/CGStmtOpenMP.cpp

@@ -5556,12 +5556,14 @@ void CodeGenFunction::EmitOMPDepobjDirective(const OMPDepobjDirective &S) {
   const auto *DO = S.getSingleClause<OMPDepobjClause>();
   LValue DOLVal = EmitLValue(DO->getDepobj());
   if (const auto *DC = S.getSingleClause<OMPDependClause>()) {
-    OMPTaskDataTy::DependData Dependencies(DC->getDependencyKind(),
-                                           DC->getModifier());
-    Dependencies.DepExprs.append(DC->varlist_begin(), DC->varlist_end());
-    Address DepAddr = CGM.getOpenMPRuntime().emitDepobjDependClause(
-        *this, Dependencies, DC->getBeginLoc());
-    EmitStoreOfScalar(DepAddr.emitRawPointer(*this), DOLVal);
+    // Build list and emit dependences
+    OMPTaskDataTy Data;
+    buildDependences(S, Data);
+    for (auto &Dep : Data.Dependences) {
+      Address DepAddr = CGM.getOpenMPRuntime().emitDepobjDependClause(
+          *this, Dep, DC->getBeginLoc());
+      EmitStoreOfScalar(DepAddr.emitRawPointer(*this), DOLVal);
+    }
     return;
   }
   if (const auto *DC = S.getSingleClause<OMPDestroyClause>()) {

clang/lib/Headers/openmp_wrappers/complex_cmath.h

@@ -64,8 +64,13 @@ template <class _Tp> __DEVICE__ _Tp norm(const std::complex<_Tp> &__c) {
 }
 
 // conj
-
-template <class _Tp> std::complex<_Tp> conj(const std::complex<_Tp> &__c) {
+#ifdef _GLIBCXX20_CONSTEXPR
+#define CXX20_CONSTEXPR_DEVICE __DEVICE__
+#else
+#define CXX20_CONSTEXPR_DEVICE
+#endif
+template <class _Tp>
+CXX20_CONSTEXPR_DEVICE std::complex<_Tp> conj(const std::complex<_Tp> &__c) {
   return std::complex<_Tp>(__c.real(), -__c.imag());
 }
 

clang/test/OpenMP/depobj_codegen.cpp

@@ -17,6 +17,15 @@
 typedef void *omp_depend_t;
 
 void foo() {}
+void tmainc(){
+   omp_depend_t obj;
+#pragma omp depobj(obj) depend(inout: omp_all_memory)
+{
+   volatile omp_depend_t temp = obj;
+   char* char_ptr = reinterpret_cast<char*>(temp);
+   char_ptr[0] = 1;
+}
+}
 
 template <class T>
 T tmain(T argc) {
@@ -35,10 +44,25 @@ int main(int argc, char **argv) {
 #pragma omp depobj(b) destroy
 #pragma omp depobj(b) update(mutexinoutset)
 #pragma omp depobj(a) depend(iterator(char *p = argv[argc]:argv[0]:-1), out: p[0])
-  (void)tmain(a), tmain(b);
+ (void)tmain(a), tmain(b);
+ tmainc();
   return 0;
 }
-
+// CHECK-LABEL: tmainc
+// CHECK: [[D_ADDR:%obj]] = alloca ptr,
+// CHECK: [[GTID:%.+]] = call i32 @__kmpc_global_thread_num(
+// CHECK: [[DEP_ADDR_ADDR2:%.+]] = call ptr @__kmpc_alloc(i32 [[GTID]], i64 48, ptr null)
+// CHECK: [[SZ_DEOOBJ:%.+]] = getelementptr inbounds nuw %struct.kmp_depend_info, ptr [[DEP_ADDR_ADDR2]], i{{.+}} 0, i{{.+}} 0
+// CHECK: store i64 1, ptr [[SZ_DEOOBJ]], align 8
+// CHECK: [[DEPOBJ_BASE_ADDR:%.+]] = getelementptr %struct.kmp_depend_info, ptr [[DEP_ADDR_ADDR2]], i{{.+}} 1
+// CHECK: [[ADDR_ONE:%.+]] = getelementptr inbounds nuw %struct.kmp_depend_info, ptr [[DEPOBJ_BASE_ADDR]], i{{.+}} 0, i{{.+}} 0
+// CHECK: store i64 0, ptr [[ADDR_ONE]], align 8
+// CHECK: [[SZ_ADDR:%.+]] = getelementptr inbounds nuw %struct.kmp_depend_info, ptr [[DEPOBJ_BASE_ADDR]], i{{.+}} 0, i{{.+}} 1
+// CHECK: store i64 0, ptr [[SZ_ADDR]], align 8
+// CHECK: [[SZ_ADDR_NEW:%.+]] = getelementptr inbounds nuw %struct.kmp_depend_info, ptr [[DEPOBJ_BASE_ADDR]], i{{.+}} 0, i{{.+}} 2
+// CHECK: store {{i[0-9]+}} {{-?[0-9]+}}, ptr [[SZ_ADDR_NEW]], align 8
+// CHECK: [[DEP_NEW:%.+]] = getelementptr   %struct.kmp_depend_info, ptr [[DEP_ADDR_ADDR2]], i{{.+}} 1
+// CHECK: store ptr [[DEP_NEW]], ptr [[D_ADDR]], align 8
 // CHECK-LABEL: @main
 // CHECK: [[B_ADDR:%b]] = alloca ptr,
 // CHECK: [[GTID:%.+]] = call i32 @__kmpc_global_thread_num(
@@ -69,6 +93,8 @@ int main(int argc, char **argv) {
 // CHECK: [[NUMDEPS_ADDR:%.+]] = getelementptr inbounds nuw %struct.kmp_depend_info, ptr [[NUMDEPS_BASE]], i{{.+}} 0, i{{.+}} 0
 // CHECK: [[NUMDEPS:%.+]] = load i64, ptr [[NUMDEPS_ADDR]], align 8
 // CHECK: [[END:%.+]] = getelementptr %struct.kmp_depend_info, ptr [[B_BASE]], i64 [[NUMDEPS]]
+
+
 // CHECK: br label %[[BODY:.+]]
 // CHECK: [[BODY]]:
 // CHECK: [[EL:%.+]] = phi ptr [ [[B_BASE]], %{{.+}} ], [ [[EL_NEXT:%.+]], %[[BODY]] ]
@@ -228,6 +254,8 @@ int main(int argc, char **argv) {
 // CHECK: [[EL_NEXT]] = getelementptr %struct.kmp_depend_info, ptr [[EL]], i{{.+}} 1
 // CHECK: [[IS_DONE:%.+]] = icmp eq ptr [[EL_NEXT]], [[END]]
 // CHECK: br i1 [[IS_DONE]], label %[[DONE:.+]], label %[[BODY]]
+
 // CHECK: [[DONE]]:
 
+
 #endif

clang/test/Sema/aarch64-incompat-sm-builtin-calls.c

@@ -28,6 +28,16 @@ void incompat_sme_smc(svbool_t pg, void const *ptr) __arm_streaming_compatible _
   return __builtin_sme_svld1_hor_za128(0, 0, pg, ptr);
 }
 
+float incomp_sve_sm_fadda_sm(void) __arm_streaming {
+  // expected-error@+1 {{builtin can only be called from a non-streaming function}}
+  return svadda(svptrue_b32(), 0, svdup_f32(1));
+}
+
+float incomp_sve_sm_fadda_smc(void) __arm_streaming_compatible {
+  // expected-error@+1 {{builtin can only be called from a non-streaming function}}
+  return svadda(svptrue_b32(), 0, svdup_f32(1));
+}
+
 svuint32_t incompat_sve_sm(svbool_t pg, svuint32_t a, int16_t b) __arm_streaming {
   // expected-error@+1 {{builtin can only be called from a non-streaming function}}
   return __builtin_sve_svld1_gather_u32base_index_u32(pg, a, b);

lldb/test/API/python_api/process/cancel_attach/TestCancelAttach.py

@@ -14,6 +14,11 @@
 class AttachCancelTestCase(TestBase):
     NO_DEBUG_INFO_TESTCASE = True
 
+    @skipIf(
+        remote=True,
+        hostoslist=["windows"],
+        bugnumber="https://github.com/llvm/llvm-project/issues/115618",
+    )
     def test_scripted_implementation(self):
         """Test that cancelling a stuck "attach waitfor" works."""
         # First make an empty target for the attach:

llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp

@@ -3920,6 +3920,19 @@ KnownBits SelectionDAG::computeKnownBits(SDValue Op, const APInt &DemandedElts,
     Known.Zero.setBitsFrom(1);
     break;
   }
+  case ISD::MGATHER:
+  case ISD::MLOAD: {
+    ISD::LoadExtType ETy =
+        (Opcode == ISD::MGATHER)
+            ? cast<MaskedGatherSDNode>(Op)->getExtensionType()
+            : cast<MaskedLoadSDNode>(Op)->getExtensionType();
+    if (ETy == ISD::ZEXTLOAD) {
+      EVT MemVT = cast<MemSDNode>(Op)->getMemoryVT();
+      KnownBits Known0(MemVT.getScalarSizeInBits());
+      return Known0.zext(BitWidth);
+    }
+    break;
+  }
   case ISD::LOAD: {
     LoadSDNode *LD = cast<LoadSDNode>(Op);
     const Constant *Cst = TLI->getTargetConstantFromLoad(LD);

llvm/lib/Target/LoongArch/MCTargetDesc/LoongArchMCTargetDesc.cpp

@@ -55,7 +55,7 @@ static MCInstrInfo *createLoongArchMCInstrInfo() {
 static MCSubtargetInfo *
 createLoongArchMCSubtargetInfo(const Triple &TT, StringRef CPU, StringRef FS) {
   if (CPU.empty() || CPU == "generic")
-    CPU = TT.isArch64Bit() ? "la464" : "generic-la32";
+    CPU = TT.isArch64Bit() ? "generic-la64" : "generic-la32";
   return createLoongArchMCSubtargetInfoImpl(TT, CPU, /*TuneCPU*/ CPU, FS);
 }
 

llvm/lib/Target/X86/X86PfmCounters.td

@@ -189,13 +189,13 @@ def IceLakePfmCounters : ProcPfmCounters {
   let CycleCounter = UnhaltedCoreCyclesPfmCounter;
   let UopsCounter = UopsIssuedPfmCounter;
   let IssueCounters = [
-    PfmIssueCounter<"ICXPort0",  "uops_dispatched_port:port_0">,
-    PfmIssueCounter<"ICXPort1",  "uops_dispatched_port:port_1">,
-    PfmIssueCounter<"ICXPort23", "uops_dispatched_port:port_2_3">,
-    PfmIssueCounter<"ICXPort49", "uops_dispatched_port:port_4_9">,
-    PfmIssueCounter<"ICXPort5",  "uops_dispatched_port:port_5">,
-    PfmIssueCounter<"ICXPort6",  "uops_dispatched_port:port_6">,
-    PfmIssueCounter<"ICXPort78", "uops_dispatched_port:port_7_8">
+    PfmIssueCounter<"ICXPort0",  "uops_dispatched:port_0">,
+    PfmIssueCounter<"ICXPort1",  "uops_dispatched:port_1">,
+    PfmIssueCounter<"ICXPort23", "uops_dispatched:port_2_3">,
+    PfmIssueCounter<"ICXPort49", "uops_dispatched:port_4_9">,
+    PfmIssueCounter<"ICXPort5",  "uops_dispatched:port_5">,
+    PfmIssueCounter<"ICXPort6",  "uops_dispatched:port_6">,
+    PfmIssueCounter<"ICXPort78", "uops_dispatched:port_7_8">
   ];
   let ValidationCounters = DefaultIntelPfmValidationCounters;
 }
@@ -208,16 +208,16 @@ def AlderLakePfmCounters : ProcPfmCounters {
   let CycleCounter = UnhaltedCoreCyclesPfmCounter;
   let UopsCounter = UopsIssuedPfmCounter;
   let IssueCounters = [
-    PfmIssueCounter<"ADLPPort00", "uops_dispatched_port:port_0">,
-    PfmIssueCounter<"ADLPPort01", "uops_dispatched_port:port_1">,
+    PfmIssueCounter<"ADLPPort00", "uops_dispatched:port_0">,
+    PfmIssueCounter<"ADLPPort01", "uops_dispatched:port_1">,
     // The perfmon documentation and thus libpfm seems to incorrectly label
     // this performance counter, as ports 2,3, and 11 are actually grouped
     // according to most documentation. See #113941 for additional details.
-    PfmIssueCounter<"ADLPPort02_03_11", "uops_dispatched_port:port_2_3_10">,
-    PfmIssueCounter<"ADLPPort04_09", "uops_dispatched_port:port_4_9">,
-    PfmIssueCounter<"ADLPPort05_11", "uops_dispatched_port:port_5_11">,
-    PfmIssueCounter<"ADLPPort06", "uops_dispatched_port:port_6">,
-    PfmIssueCounter<"ADLPPort07_08", "uops_dispatched_port:port_7_8">
+    PfmIssueCounter<"ADLPPort02_03_11", "uops_dispatched:port_2_3_10">,
+    PfmIssueCounter<"ADLPPort04_09", "uops_dispatched:port_4_9">,
+    PfmIssueCounter<"ADLPPort05_11", "uops_dispatched:port_5_11">,
+    PfmIssueCounter<"ADLPPort06", "uops_dispatched:port_6">,
+    PfmIssueCounter<"ADLPPort07_08", "uops_dispatched:port_7_8">
   ];
   let ValidationCounters = DefaultIntelPfmValidationCounters;
 }
@@ -227,16 +227,16 @@ def SapphireRapidsPfmCounters : ProcPfmCounters {
   let CycleCounter = UnhaltedCoreCyclesPfmCounter;
   let UopsCounter = UopsIssuedPfmCounter;
   let IssueCounters = [
-    PfmIssueCounter<"SPRPort00", "uops_dispatched_port:port_0">,
-    PfmIssueCounter<"SPRPort01", "uops_dispatched_port:port_1">,
+    PfmIssueCounter<"SPRPort00", "uops_dispatched:port_0">,
+    PfmIssueCounter<"SPRPort01", "uops_dispatched:port_1">,
     // The perfmon documentation and thus libpfm seems to incorrectly label
     // this performance counter, as ports 2,3, and 11 are actually grouped
     // according to most documentation. See #113941 for additional details.
-    PfmIssueCounter<"SPRPort02_03_11", "uops_dispatched_port:port_2_3_10">,
-    PfmIssueCounter<"SPRPort04_09", "uops_dispatched_port:port_4_9">,
-    PfmIssueCounter<"SPRPort05_11", "uops_dispatched_port:port_5_11">,
-    PfmIssueCounter<"SPRPort06", "uops_dispatched_port:port_6">,
-    PfmIssueCounter<"SPRPort07_08", "uops_dispatched_port:port_7_8">,
+    PfmIssueCounter<"SPRPort02_03_11", "uops_dispatched:port_2_3_10">,
+    PfmIssueCounter<"SPRPort04_09", "uops_dispatched:port_4_9">,
+    PfmIssueCounter<"SPRPort05_11", "uops_dispatched:port_5_11">,
+    PfmIssueCounter<"SPRPort06", "uops_dispatched:port_6">,
+    PfmIssueCounter<"SPRPort07_08", "uops_dispatched:port_7_8">,
   ];
   let ValidationCounters = DefaultIntelPfmValidationCounters;
 }

llvm/test/CodeGen/AArch64/sve-hadd.ll

@@ -1347,10 +1347,8 @@ define void @zext_mload_avgflooru(ptr %p1, ptr %p2, <vscale x 8 x i1> %mask) {
 ; SVE:       // %bb.0:
 ; SVE-NEXT:    ld1b { z0.h }, p0/z, [x0]
 ; SVE-NEXT:    ld1b { z1.h }, p0/z, [x1]
-; SVE-NEXT:    eor z2.d, z0.d, z1.d
-; SVE-NEXT:    and z0.d, z0.d, z1.d
-; SVE-NEXT:    lsr z1.h, z2.h, #1
 ; SVE-NEXT:    add z0.h, z0.h, z1.h
+; SVE-NEXT:    lsr z0.h, z0.h, #1
 ; SVE-NEXT:    st1h { z0.h }, p0, [x0]
 ; SVE-NEXT:    ret
 ;
@@ -1377,11 +1375,11 @@ define void @zext_mload_avgceilu(ptr %p1, ptr %p2, <vscale x 8 x i1> %mask) {
 ; SVE-LABEL: zext_mload_avgceilu:
 ; SVE:       // %bb.0:
 ; SVE-NEXT:    ld1b { z0.h }, p0/z, [x0]
-; SVE-NEXT:    ld1b { z1.h }, p0/z, [x1]
-; SVE-NEXT:    eor z2.d, z0.d, z1.d
-; SVE-NEXT:    orr z0.d, z0.d, z1.d
-; SVE-NEXT:    lsr z1.h, z2.h, #1
-; SVE-NEXT:    sub z0.h, z0.h, z1.h
+; SVE-NEXT:    mov z1.h, #-1 // =0xffffffffffffffff
+; SVE-NEXT:    ld1b { z2.h }, p0/z, [x1]
+; SVE-NEXT:    eor z0.d, z0.d, z1.d
+; SVE-NEXT:    sub z0.h, z2.h, z0.h
+; SVE-NEXT:    lsr z0.h, z0.h, #1
 ; SVE-NEXT:    st1b { z0.h }, p0, [x0]
 ; SVE-NEXT:    ret
 ;