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[AMDGPU] Prevent folding of flat_scr_base_hi into a 64-bit SALU (#170373)
Fixes: SWDEV-563886
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‎llvm/lib/Target/AMDGPU/GCNSubtarget.h‎

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@@ -1868,6 +1868,12 @@ class GCNSubtarget final : public AMDGPUGenSubtargetInfo,
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return GFX1250Insts && getGeneration() == GFX12;
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}
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// src_flat_scratch_hi cannot be used as a source in SALU producing a 64-bit
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// result.
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bool hasFlatScratchHiInB64InstHazard() const {
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return GFX1250Insts && getGeneration() == GFX12;
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}
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/// \returns true if the subtarget supports clusters of workgroups.
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bool hasClusters() const { return HasClusters; }
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‎llvm/lib/Target/AMDGPU/SIInstrInfo.cpp‎

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@@ -6256,6 +6256,17 @@ bool SIInstrInfo::isLegalRegOperand(const MachineInstr &MI, unsigned OpIdx,
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(int)OpIdx == AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::src0) &&
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RI.isSGPRReg(MRI, MO.getReg()))
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return false;
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if (ST.hasFlatScratchHiInB64InstHazard() &&
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MO.getReg() == AMDGPU::SRC_FLAT_SCRATCH_BASE_HI && isSALU(MI)) {
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if (const MachineOperand *Dst = getNamedOperand(MI, AMDGPU::OpName::sdst)) {
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if (AMDGPU::getRegBitWidth(*MRI.getRegClass(Dst->getReg())) == 64)
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return false;
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}
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if (Opc == AMDGPU::S_BITCMP0_B64 || Opc == AMDGPU::S_BITCMP1_B64)
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return false;
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}
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return true;
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}
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‎llvm/test/CodeGen/AMDGPU/hazard-gfx1250-flat-scr-hi.mir‎

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@@ -0,0 +1,145 @@
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# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 6
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# RUN: llc -mtriple=amdgcn -mcpu=gfx1250 -run-pass si-fold-operands %s -o - | FileCheck -check-prefix=GCN %s
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---
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name: s_ashr_i64
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tracksRegLiveness: true
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body: |
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bb.0:
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; GCN-LABEL: name: s_ashr_i64
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; GCN: [[COPY:%[0-9]+]]:sreg_32 = COPY $src_flat_scratch_base_hi
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; GCN-NEXT: [[S_ASHR_I64_:%[0-9]+]]:sreg_64 = S_ASHR_I64 undef %2:sreg_64, [[COPY]], implicit-def $scc
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%0:sreg_32 = COPY $src_flat_scratch_base_hi
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%2:sreg_64 = S_ASHR_I64 undef %1:sreg_64, %0, implicit-def $scc
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...
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---
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name: s_lshl_b64
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tracksRegLiveness: true
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body: |
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bb.0:
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; GCN-LABEL: name: s_lshl_b64
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; GCN: [[COPY:%[0-9]+]]:sreg_32 = COPY $src_flat_scratch_base_hi
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; GCN-NEXT: [[S_LSHL_B64_:%[0-9]+]]:sreg_64 = S_LSHL_B64 undef %2:sreg_64, [[COPY]], implicit-def $scc
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%0:sreg_32 = COPY $src_flat_scratch_base_hi
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%2:sreg_64 = S_LSHL_B64 undef %1:sreg_64, %0, implicit-def $scc
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...
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---
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name: s_lshr_b64
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tracksRegLiveness: true
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body: |
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bb.0:
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; GCN-LABEL: name: s_lshr_b64
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; GCN: [[COPY:%[0-9]+]]:sreg_32 = COPY $src_flat_scratch_base_hi
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; GCN-NEXT: [[S_LSHR_B64_:%[0-9]+]]:sreg_64 = S_LSHR_B64 undef %2:sreg_64, [[COPY]], implicit-def $scc
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%0:sreg_32 = COPY $src_flat_scratch_base_hi
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%2:sreg_64 = S_LSHR_B64 undef %1:sreg_64, %0, implicit-def $scc
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...
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---
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name: s_bfe_i64
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tracksRegLiveness: true
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body: |
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bb.0:
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; GCN-LABEL: name: s_bfe_i64
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; GCN: [[COPY:%[0-9]+]]:sreg_32 = COPY $src_flat_scratch_base_hi
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; GCN-NEXT: [[S_BFE_I64_:%[0-9]+]]:sreg_64 = S_BFE_I64 undef %2:sreg_64, [[COPY]], implicit-def $scc
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%0:sreg_32 = COPY $src_flat_scratch_base_hi
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%2:sreg_64 = S_BFE_I64 undef %1:sreg_64, %0, implicit-def $scc
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...
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---
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name: s_bfe_u64
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tracksRegLiveness: true
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body: |
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bb.0:
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; GCN-LABEL: name: s_bfe_u64
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; GCN: [[COPY:%[0-9]+]]:sreg_32 = COPY $src_flat_scratch_base_hi
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; GCN-NEXT: [[S_BFE_U64_:%[0-9]+]]:sreg_64 = S_BFE_U64 undef %2:sreg_64, [[COPY]], implicit-def $scc
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%0:sreg_32 = COPY $src_flat_scratch_base_hi
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%2:sreg_64 = S_BFE_U64 undef %1:sreg_64, %0, implicit-def $scc
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...
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---
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name: s_bfm_b64
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tracksRegLiveness: true
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body: |
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bb.0:
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; GCN-LABEL: name: s_bfm_b64
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; GCN: [[COPY:%[0-9]+]]:sreg_32 = COPY $src_flat_scratch_base_hi
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; GCN-NEXT: [[S_BFM_B64_:%[0-9]+]]:sreg_64 = S_BFM_B64 [[COPY]], 1, implicit-def $scc
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%0:sreg_32 = COPY $src_flat_scratch_base_hi
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%1:sreg_64 = S_BFM_B64 %0, 1, implicit-def $scc
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...
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---
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name: s_bitcmp0_b64
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tracksRegLiveness: true
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body: |
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bb.0:
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; GCN-LABEL: name: s_bitcmp0_b64
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; GCN: [[COPY:%[0-9]+]]:sreg_32 = COPY $src_flat_scratch_base_hi
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; GCN-NEXT: S_BITCMP0_B64 undef %1:sreg_64, [[COPY]], implicit undef $scc, implicit-def $scc
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%0:sreg_32 = COPY $src_flat_scratch_base_hi
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S_BITCMP0_B64 undef %1:sreg_64, %0, implicit undef $scc, implicit-def $scc
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...
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---
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name: s_bitcmp1_b64
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tracksRegLiveness: true
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body: |
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bb.0:
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; GCN-LABEL: name: s_bitcmp1_b64
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; GCN: [[COPY:%[0-9]+]]:sreg_32 = COPY $src_flat_scratch_base_hi
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; GCN-NEXT: S_BITCMP1_B64 undef %1:sreg_64, [[COPY]], implicit undef $scc, implicit-def $scc
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%0:sreg_32 = COPY $src_flat_scratch_base_hi
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S_BITCMP1_B64 undef %1:sreg_64, %0, implicit undef $scc, implicit-def $scc
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...
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---
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name: s_bitreplicate_b64_b32
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tracksRegLiveness: true
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body: |
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bb.0:
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; GCN-LABEL: name: s_bitreplicate_b64_b32
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; GCN: [[COPY:%[0-9]+]]:sreg_32 = COPY $src_flat_scratch_base_hi
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; GCN-NEXT: [[S_BITREPLICATE_B64_B32_:%[0-9]+]]:sreg_64 = S_BITREPLICATE_B64_B32 [[COPY]], implicit-def $scc
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%0:sreg_32 = COPY $src_flat_scratch_base_hi
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%2:sreg_64 = S_BITREPLICATE_B64_B32 %0, implicit-def $scc
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...
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---
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name: s_bitset0_b64
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tracksRegLiveness: true
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body: |
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bb.0:
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; GCN-LABEL: name: s_bitset0_b64
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; GCN: [[COPY:%[0-9]+]]:sreg_32 = COPY $src_flat_scratch_base_hi
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; GCN-NEXT: [[S_BITSET0_B64_:%[0-9]+]]:sreg_64 = S_BITSET0_B64 [[COPY]], undef [[S_BITSET0_B64_]], implicit-def $scc
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%0:sreg_32 = COPY $src_flat_scratch_base_hi
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%1:sreg_64 = S_BITSET0_B64 %0, undef %1:sreg_64, implicit-def $scc
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...
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---
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name: s_bitset1_b64
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tracksRegLiveness: true
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body: |
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bb.0:
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; GCN-LABEL: name: s_bitset1_b64
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; GCN: [[COPY:%[0-9]+]]:sreg_32 = COPY $src_flat_scratch_base_hi
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; GCN-NEXT: [[S_BITSET1_B64_:%[0-9]+]]:sreg_64 = S_BITSET1_B64 [[COPY]], undef [[S_BITSET1_B64_]], implicit-def $scc
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%0:sreg_32 = COPY $src_flat_scratch_base_hi
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%1:sreg_64 = S_BITSET1_B64 %0, undef %1:sreg_64, implicit-def $scc
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...

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