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[RISCV] Add ISel patterns for Xqciac QC.MULIADD instruction (#147661)
Add basic isel patterns for the multiple accumulate QC.MULIADD instruction. While most case work with just the TD file pattern, there are few cases which need to be handled in ISelLowering depending on the immediate we are multiplying with: - imm + 1 , imm - 1, 1 - imm, -1 - imm are a power of 2 --> these become slli and add/sub - immediate is 2^n - 2 ^m --> this becomes (add/sub (shl X, C1), (shl X, C2)) - imm - 2, imm - 4, imm - 6 is a power of 2 --> these use shxadd when zba is enabled The patch does not decompose mul if Xqciac is present, for the above conditions. There could be cases where this may not beneficial which I plan to address in follow up patches.
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‎llvm/lib/Target/RISCV/RISCVISelLowering.cpp‎

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Original file line numberDiff line numberDiff line change
@@ -15993,6 +15993,10 @@ static SDValue expandMul(SDNode *N, SelectionDAG &DAG,
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return SDValue();
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uint64_t MulAmt = CNode->getZExtValue();
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// Don't do this if the Xqciac extension is enabled and the MulAmt in simm12.
15997+
if (Subtarget.hasVendorXqciac() && isInt<12>(MulAmt))
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return SDValue();
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const bool HasShlAdd = Subtarget.hasStdExtZba() ||
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Subtarget.hasVendorXTHeadBa() ||
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Subtarget.hasVendorXAndesPerf();
@@ -23752,6 +23756,10 @@ bool RISCVTargetLowering::decomposeMulByConstant(LLVMContext &Context, EVT VT,
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auto *ConstNode = cast<ConstantSDNode>(C);
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const APInt &Imm = ConstNode->getAPIntValue();
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// Don't do this if the Xqciac extension is enabled and the Imm in simm12.
23760+
if (Subtarget.hasVendorXqciac() && Imm.isSignedIntN(12))
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return false;
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// Break the MUL to a SLLI and an ADD/SUB.
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if ((Imm + 1).isPowerOf2() || (Imm - 1).isPowerOf2() ||
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(1 - Imm).isPowerOf2() || (-1 - Imm).isPowerOf2())

‎llvm/lib/Target/RISCV/RISCVInstrInfoXqci.td‎

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Original file line numberDiff line numberDiff line change
@@ -1356,6 +1356,11 @@ class SelectQCbi<CondCode Cond, DAGOperand InTyImm, Pseudo OpNode >
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(OpNode GPRNoX0:$lhs, InTyImm:$Constant,
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(IntCCtoRISCVCC $cc), GPRNoX0:$truev, GPRNoX0:$falsev)>;
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let Predicates = [HasVendorXqciac, IsRV32] in {
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def : Pat<(XLenVT (add GPRNoX0:$rd, (mul GPRNoX0:$rs1, simm12:$imm12))),
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(QC_MULIADD GPRNoX0:$rd, GPRNoX0:$rs1, simm12:$imm12)>;
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} // Predicates = [HasVendorXqciac, IsRV32]
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/// Simple arithmetic operations
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let Predicates = [HasVendorXqcilia, IsRV32] in {

‎llvm/test/CodeGen/RISCV/xqciac.ll‎

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@@ -0,0 +1,271 @@
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; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5
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; RUN: llc -mtriple=riscv32 -mattr=+m -verify-machineinstrs < %s \
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; RUN: | FileCheck %s -check-prefix=RV32IM
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; RUN: llc -mtriple=riscv32 -mattr=+m,+experimental-xqciac -verify-machineinstrs < %s \
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; RUN: | FileCheck %s -check-prefix=RV32IMXQCIAC
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; RUN: llc -mtriple=riscv32 -mattr=+m,+experimental-xqciac,+zba -verify-machineinstrs < %s \
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; RUN: | FileCheck %s -check-prefix=RV32IZBAMXQCIAC
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define dso_local i32 @mul(i32 %a, i32 %b) local_unnamed_addr #0 {
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; RV32IM-LABEL: mul:
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; RV32IM: # %bb.0: # %entry
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; RV32IM-NEXT: slli a0, a1, 5
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; RV32IM-NEXT: add a0, a0, a1
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; RV32IM-NEXT: ret
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;
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; RV32IMXQCIAC-LABEL: mul:
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; RV32IMXQCIAC: # %bb.0: # %entry
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; RV32IMXQCIAC-NEXT: li a0, 33
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; RV32IMXQCIAC-NEXT: mul a0, a1, a0
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; RV32IMXQCIAC-NEXT: ret
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;
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; RV32IZBAMXQCIAC-LABEL: mul:
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; RV32IZBAMXQCIAC: # %bb.0: # %entry
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; RV32IZBAMXQCIAC-NEXT: li a0, 33
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; RV32IZBAMXQCIAC-NEXT: mul a0, a1, a0
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; RV32IZBAMXQCIAC-NEXT: ret
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entry:
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%mul = mul nsw i32 %b, 33
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ret i32 %mul
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}
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define dso_local i32 @muliadd(i32 %a, i32 %b) local_unnamed_addr #0 {
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; RV32IM-LABEL: muliadd:
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; RV32IM: # %bb.0: # %entry
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; RV32IM-NEXT: li a2, 165
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; RV32IM-NEXT: mul a1, a1, a2
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; RV32IM-NEXT: add a0, a1, a0
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; RV32IM-NEXT: ret
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;
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; RV32IMXQCIAC-LABEL: muliadd:
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; RV32IMXQCIAC: # %bb.0: # %entry
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; RV32IMXQCIAC-NEXT: qc.muliadd a0, a1, 165
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; RV32IMXQCIAC-NEXT: ret
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;
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; RV32IZBAMXQCIAC-LABEL: muliadd:
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; RV32IZBAMXQCIAC: # %bb.0: # %entry
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; RV32IZBAMXQCIAC-NEXT: qc.muliadd a0, a1, 165
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; RV32IZBAMXQCIAC-NEXT: ret
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entry:
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%mul = mul nsw i32 %b, 165
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%add = add nsw i32 %mul, %a
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ret i32 %add
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}
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define dso_local i32 @muliadd2(i32 %a, i32 %b) local_unnamed_addr #0 {
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; RV32IM-LABEL: muliadd2:
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; RV32IM: # %bb.0: # %entry
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; RV32IM-NEXT: li a2, 1111
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; RV32IM-NEXT: mul a1, a1, a2
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; RV32IM-NEXT: add a0, a1, a0
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; RV32IM-NEXT: ret
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;
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; RV32IMXQCIAC-LABEL: muliadd2:
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; RV32IMXQCIAC: # %bb.0: # %entry
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; RV32IMXQCIAC-NEXT: qc.muliadd a0, a1, 1111
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; RV32IMXQCIAC-NEXT: ret
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;
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; RV32IZBAMXQCIAC-LABEL: muliadd2:
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; RV32IZBAMXQCIAC: # %bb.0: # %entry
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; RV32IZBAMXQCIAC-NEXT: qc.muliadd a0, a1, 1111
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; RV32IZBAMXQCIAC-NEXT: ret
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entry:
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%mul = mul nsw i32 %b, 1111
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%add = add nsw i32 %mul, %a
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ret i32 %add
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}
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define dso_local i32 @muliadd_neg(i32 %a, i32 %b) local_unnamed_addr #0 {
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; RV32IM-LABEL: muliadd_neg:
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; RV32IM: # %bb.0: # %entry
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; RV32IM-NEXT: li a2, -165
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; RV32IM-NEXT: mul a1, a1, a2
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; RV32IM-NEXT: add a0, a1, a0
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; RV32IM-NEXT: ret
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;
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; RV32IMXQCIAC-LABEL: muliadd_neg:
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; RV32IMXQCIAC: # %bb.0: # %entry
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; RV32IMXQCIAC-NEXT: qc.muliadd a0, a1, -165
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; RV32IMXQCIAC-NEXT: ret
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;
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; RV32IZBAMXQCIAC-LABEL: muliadd_neg:
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; RV32IZBAMXQCIAC: # %bb.0: # %entry
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; RV32IZBAMXQCIAC-NEXT: qc.muliadd a0, a1, -165
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; RV32IZBAMXQCIAC-NEXT: ret
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entry:
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%mul = mul nsw i32 %b, -165
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%add = add nsw i32 %mul, %a
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ret i32 %add
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}
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define dso_local i32 @muliadd_neg2(i32 %a, i32 %b) local_unnamed_addr #0 {
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; RV32IM-LABEL: muliadd_neg2:
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; RV32IM: # %bb.0: # %entry
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; RV32IM-NEXT: li a2, -2045
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; RV32IM-NEXT: mul a1, a1, a2
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; RV32IM-NEXT: add a0, a1, a0
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; RV32IM-NEXT: ret
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;
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; RV32IMXQCIAC-LABEL: muliadd_neg2:
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; RV32IMXQCIAC: # %bb.0: # %entry
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; RV32IMXQCIAC-NEXT: qc.muliadd a0, a1, -2045
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; RV32IMXQCIAC-NEXT: ret
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;
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; RV32IZBAMXQCIAC-LABEL: muliadd_neg2:
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; RV32IZBAMXQCIAC: # %bb.0: # %entry
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; RV32IZBAMXQCIAC-NEXT: qc.muliadd a0, a1, -2045
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; RV32IZBAMXQCIAC-NEXT: ret
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entry:
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%mul = mul nsw i32 %b, -2045
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%add = add nsw i32 %mul, %a
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ret i32 %add
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}
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define dso_local i32 @pow2immplus1(i32 %a, i32 %b) local_unnamed_addr #0 {
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; RV32IM-LABEL: pow2immplus1:
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; RV32IM: # %bb.0: # %entry
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; RV32IM-NEXT: slli a2, a1, 5
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; RV32IM-NEXT: add a0, a1, a0
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; RV32IM-NEXT: add a0, a2, a0
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; RV32IM-NEXT: ret
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;
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; RV32IMXQCIAC-LABEL: pow2immplus1:
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; RV32IMXQCIAC: # %bb.0: # %entry
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; RV32IMXQCIAC-NEXT: qc.muliadd a0, a1, 33
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; RV32IMXQCIAC-NEXT: ret
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;
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; RV32IZBAMXQCIAC-LABEL: pow2immplus1:
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; RV32IZBAMXQCIAC: # %bb.0: # %entry
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; RV32IZBAMXQCIAC-NEXT: qc.muliadd a0, a1, 33
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; RV32IZBAMXQCIAC-NEXT: ret
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entry:
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%mul = mul nsw i32 %b, 33
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%add = add nsw i32 %mul, %a
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ret i32 %add
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}
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define dso_local i32 @pow2immminus2(i32 %a, i32 %b) local_unnamed_addr #0 {
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; RV32IM-LABEL: pow2immminus2:
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; RV32IM: # %bb.0: # %entry
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; RV32IM-NEXT: slli a2, a1, 1
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; RV32IM-NEXT: slli a1, a1, 7
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; RV32IM-NEXT: sub a1, a1, a2
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; RV32IM-NEXT: add a0, a1, a0
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; RV32IM-NEXT: ret
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;
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; RV32IMXQCIAC-LABEL: pow2immminus2:
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; RV32IMXQCIAC: # %bb.0: # %entry
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; RV32IMXQCIAC-NEXT: qc.muliadd a0, a1, 126
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; RV32IMXQCIAC-NEXT: ret
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;
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; RV32IZBAMXQCIAC-LABEL: pow2immminus2:
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; RV32IZBAMXQCIAC: # %bb.0: # %entry
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; RV32IZBAMXQCIAC-NEXT: qc.muliadd a0, a1, 126
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; RV32IZBAMXQCIAC-NEXT: ret
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entry:
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%mul = mul nsw i32 %b, 126
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%add = add nsw i32 %mul, %a
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ret i32 %add
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}
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define dso_local i32 @pow2minuspow2(i32 %a, i32 %b) local_unnamed_addr #0 {
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; RV32IM-LABEL: pow2minuspow2:
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; RV32IM: # %bb.0: # %entry
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; RV32IM-NEXT: slli a2, a1, 7
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; RV32IM-NEXT: slli a1, a1, 9
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; RV32IM-NEXT: sub a1, a1, a2
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; RV32IM-NEXT: add a0, a1, a0
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; RV32IM-NEXT: ret
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;
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; RV32IMXQCIAC-LABEL: pow2minuspow2:
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; RV32IMXQCIAC: # %bb.0: # %entry
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; RV32IMXQCIAC-NEXT: qc.muliadd a0, a1, 384
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; RV32IMXQCIAC-NEXT: ret
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;
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; RV32IZBAMXQCIAC-LABEL: pow2minuspow2:
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; RV32IZBAMXQCIAC: # %bb.0: # %entry
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; RV32IZBAMXQCIAC-NEXT: qc.muliadd a0, a1, 384
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; RV32IZBAMXQCIAC-NEXT: ret
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entry:
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%mul = mul nsw i32 %b, 384
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%add = add nsw i32 %mul, %a
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ret i32 %add
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}
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define dso_local i32 @gtsimm12(i32 %a, i32 %b) local_unnamed_addr #0 {
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; RV32IM-LABEL: gtsimm12:
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; RV32IM: # %bb.0: # %entry
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; RV32IM-NEXT: lui a2, 1
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; RV32IM-NEXT: addi a2, a2, 477
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; RV32IM-NEXT: mul a1, a1, a2
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; RV32IM-NEXT: add a0, a1, a0
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; RV32IM-NEXT: ret
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;
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; RV32IMXQCIAC-LABEL: gtsimm12:
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; RV32IMXQCIAC: # %bb.0: # %entry
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; RV32IMXQCIAC-NEXT: lui a2, 1
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; RV32IMXQCIAC-NEXT: addi a2, a2, 477
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; RV32IMXQCIAC-NEXT: mul a1, a1, a2
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; RV32IMXQCIAC-NEXT: add a0, a0, a1
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; RV32IMXQCIAC-NEXT: ret
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;
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; RV32IZBAMXQCIAC-LABEL: gtsimm12:
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; RV32IZBAMXQCIAC: # %bb.0: # %entry
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; RV32IZBAMXQCIAC-NEXT: lui a2, 1
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; RV32IZBAMXQCIAC-NEXT: addi a2, a2, 477
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; RV32IZBAMXQCIAC-NEXT: mul a1, a1, a2
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; RV32IZBAMXQCIAC-NEXT: add a0, a0, a1
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; RV32IZBAMXQCIAC-NEXT: ret
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entry:
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%mul = mul nsw i32 %b, 4573
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%add = add nsw i32 %mul, %a
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ret i32 %add
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}
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; NOTE: This will become qc.shladd once support is added
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define dso_local i32 @pow2(i32 %a, i32 %b) local_unnamed_addr #0 {
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; RV32IM-LABEL: pow2:
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; RV32IM: # %bb.0: # %entry
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; RV32IM-NEXT: slli a1, a1, 5
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; RV32IM-NEXT: add a0, a1, a0
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; RV32IM-NEXT: ret
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;
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; RV32IMXQCIAC-LABEL: pow2:
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; RV32IMXQCIAC: # %bb.0: # %entry
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; RV32IMXQCIAC-NEXT: slli a1, a1, 5
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; RV32IMXQCIAC-NEXT: add a0, a0, a1
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; RV32IMXQCIAC-NEXT: ret
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;
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; RV32IZBAMXQCIAC-LABEL: pow2:
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; RV32IZBAMXQCIAC: # %bb.0: # %entry
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; RV32IZBAMXQCIAC-NEXT: slli a1, a1, 5
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; RV32IZBAMXQCIAC-NEXT: add a0, a0, a1
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; RV32IZBAMXQCIAC-NEXT: ret
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entry:
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%mul = mul nsw i32 %b, 32
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%add = add nsw i32 %mul, %a
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ret i32 %add
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}
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define dso_local i32 @shxadd(i32 %a, i32 %b) local_unnamed_addr #0 {
251+
; RV32IM-LABEL: shxadd:
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; RV32IM: # %bb.0: # %entry
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; RV32IM-NEXT: slli a1, a1, 1
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; RV32IM-NEXT: add a0, a1, a0
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; RV32IM-NEXT: ret
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;
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; RV32IMXQCIAC-LABEL: shxadd:
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; RV32IMXQCIAC: # %bb.0: # %entry
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; RV32IMXQCIAC-NEXT: slli a1, a1, 1
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; RV32IMXQCIAC-NEXT: add a0, a0, a1
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; RV32IMXQCIAC-NEXT: ret
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;
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; RV32IZBAMXQCIAC-LABEL: shxadd:
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; RV32IZBAMXQCIAC: # %bb.0: # %entry
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; RV32IZBAMXQCIAC-NEXT: sh1add a0, a1, a0
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; RV32IZBAMXQCIAC-NEXT: ret
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entry:
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%mul = mul nsw i32 %b, 2
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%add = add nsw i32 %mul, %a
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ret i32 %add
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}

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