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‎llvm/lib/Target/RISCV/RISCVInsertVSETVLI.cpp‎

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -1809,7 +1809,7 @@ void RISCVInsertVSETVLI::insertVSETIVLIBeforeCopy(MachineBasicBlock &MBB) {
18091809
BuildMI(MBB, &MI, MI.getDebugLoc(), TII->get(RISCV::PseudoVSETIVLI))
18101810
.addReg(RISCV::X0, RegState::Define | RegState::Dead)
18111811
.addImm(0)
1812-
.addImm(RISCVVType::encodeVTYPE(RISCVII::VLMUL::LMUL_1, 32, false,
1812+
.addImm(RISCVVType::encodeVTYPE(RISCVII::VLMUL::LMUL_1, 8, false,
18131813
false));
18141814
if (LIS)
18151815
LIS->InsertMachineInstrInMaps(*VSETVL0MI);

‎llvm/test/CodeGen/RISCV/inline-asm-v-constraint.ll‎

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -45,7 +45,7 @@ define <vscale x 1 x i8> @constraint_vd(<vscale x 1 x i8> %0, <vscale x 1 x i8>
4545
define <vscale x 1 x i1> @constraint_vm(<vscale x 1 x i1> %0, <vscale x 1 x i1> %1) nounwind {
4646
; RV32I-LABEL: constraint_vm:
4747
; RV32I: # %bb.0:
48-
; RV32I-NEXT: vsetivli zero, 0, e32, m1, tu, mu
48+
; RV32I-NEXT: vsetivli zero, 0, e8, m1, tu, mu
4949
; RV32I-NEXT: vmv1r.v v9, v0
5050
; RV32I-NEXT: vmv1r.v v0, v8
5151
; RV32I-NEXT: #APP
@@ -55,7 +55,7 @@ define <vscale x 1 x i1> @constraint_vm(<vscale x 1 x i1> %0, <vscale x 1 x i1>
5555
;
5656
; RV64I-LABEL: constraint_vm:
5757
; RV64I: # %bb.0:
58-
; RV64I-NEXT: vsetivli zero, 0, e32, m1, tu, mu
58+
; RV64I-NEXT: vsetivli zero, 0, e8, m1, tu, mu
5959
; RV64I-NEXT: vmv1r.v v9, v0
6060
; RV64I-NEXT: vmv1r.v v0, v8
6161
; RV64I-NEXT: #APP

‎llvm/test/CodeGen/RISCV/rvv/abs-vp.ll‎

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -567,7 +567,7 @@ define <vscale x 16 x i64> @vp_abs_nxv16i64(<vscale x 16 x i64> %va, <vscale x 1
567567
; CHECK-NEXT: slli a1, a1, 4
568568
; CHECK-NEXT: sub sp, sp, a1
569569
; CHECK-NEXT: .cfi_escape 0x0f, 0x0d, 0x72, 0x00, 0x11, 0x10, 0x22, 0x11, 0x10, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 16 + 16 * vlenb
570-
; CHECK-NEXT: vsetivli zero, 0, e32, m1, tu, mu
570+
; CHECK-NEXT: vsetivli zero, 0, e8, m1, tu, mu
571571
; CHECK-NEXT: vmv1r.v v24, v0
572572
; CHECK-NEXT: csrr a1, vlenb
573573
; CHECK-NEXT: slli a1, a1, 3

‎llvm/test/CodeGen/RISCV/rvv/bitreverse-vp.ll‎

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -3075,7 +3075,7 @@ define <vscale x 64 x i16> @vp_bitreverse_nxv64i16(<vscale x 64 x i16> %va, <vsc
30753075
; CHECK-NEXT: slli a1, a1, 4
30763076
; CHECK-NEXT: sub sp, sp, a1
30773077
; CHECK-NEXT: .cfi_escape 0x0f, 0x0d, 0x72, 0x00, 0x11, 0x10, 0x22, 0x11, 0x10, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 16 + 16 * vlenb
3078-
; CHECK-NEXT: vsetivli zero, 0, e32, m1, tu, mu
3078+
; CHECK-NEXT: vsetivli zero, 0, e8, m1, tu, mu
30793079
; CHECK-NEXT: vmv1r.v v24, v0
30803080
; CHECK-NEXT: csrr a1, vlenb
30813081
; CHECK-NEXT: slli a1, a1, 3
@@ -3159,7 +3159,7 @@ define <vscale x 64 x i16> @vp_bitreverse_nxv64i16(<vscale x 64 x i16> %va, <vsc
31593159
;
31603160
; CHECK-ZVBB-LABEL: vp_bitreverse_nxv64i16:
31613161
; CHECK-ZVBB: # %bb.0:
3162-
; CHECK-ZVBB-NEXT: vsetivli zero, 0, e32, m1, tu, mu
3162+
; CHECK-ZVBB-NEXT: vsetivli zero, 0, e8, m1, tu, mu
31633163
; CHECK-ZVBB-NEXT: vmv1r.v v24, v0
31643164
; CHECK-ZVBB-NEXT: csrr a1, vlenb
31653165
; CHECK-ZVBB-NEXT: srli a2, a1, 1

‎llvm/test/CodeGen/RISCV/rvv/bswap-vp.ll‎

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -1584,7 +1584,7 @@ define <vscale x 64 x i16> @vp_bswap_nxv64i16(<vscale x 64 x i16> %va, <vscale x
15841584
; CHECK-NEXT: slli a1, a1, 4
15851585
; CHECK-NEXT: sub sp, sp, a1
15861586
; CHECK-NEXT: .cfi_escape 0x0f, 0x0d, 0x72, 0x00, 0x11, 0x10, 0x22, 0x11, 0x10, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 16 + 16 * vlenb
1587-
; CHECK-NEXT: vsetivli zero, 0, e32, m1, tu, mu
1587+
; CHECK-NEXT: vsetivli zero, 0, e8, m1, tu, mu
15881588
; CHECK-NEXT: vmv1r.v v24, v0
15891589
; CHECK-NEXT: csrr a1, vlenb
15901590
; CHECK-NEXT: slli a1, a1, 3
@@ -1632,7 +1632,7 @@ define <vscale x 64 x i16> @vp_bswap_nxv64i16(<vscale x 64 x i16> %va, <vscale x
16321632
;
16331633
; CHECK-ZVKB-LABEL: vp_bswap_nxv64i16:
16341634
; CHECK-ZVKB: # %bb.0:
1635-
; CHECK-ZVKB-NEXT: vsetivli zero, 0, e32, m1, tu, mu
1635+
; CHECK-ZVKB-NEXT: vsetivli zero, 0, e8, m1, tu, mu
16361636
; CHECK-ZVKB-NEXT: vmv1r.v v24, v0
16371637
; CHECK-ZVKB-NEXT: csrr a1, vlenb
16381638
; CHECK-ZVKB-NEXT: srli a2, a1, 1

‎llvm/test/CodeGen/RISCV/rvv/calling-conv-fastcc.ll‎

Lines changed: 4 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -336,7 +336,7 @@ define fastcc <vscale x 32 x i32> @ret_nxv32i32_call_nxv32i32_nxv32i32_i32(<vsca
336336
; RV32-NEXT: add a1, a3, a1
337337
; RV32-NEXT: li a3, 2
338338
; RV32-NEXT: vs8r.v v16, (a1)
339-
; RV32-NEXT: vsetivli zero, 0, e32, m1, tu, mu
339+
; RV32-NEXT: vsetivli zero, 0, e8, m1, tu, mu
340340
; RV32-NEXT: vmv8r.v v8, v0
341341
; RV32-NEXT: vmv8r.v v16, v24
342342
; RV32-NEXT: call ext2
@@ -375,7 +375,7 @@ define fastcc <vscale x 32 x i32> @ret_nxv32i32_call_nxv32i32_nxv32i32_i32(<vsca
375375
; RV64-NEXT: add a1, a3, a1
376376
; RV64-NEXT: li a3, 2
377377
; RV64-NEXT: vs8r.v v16, (a1)
378-
; RV64-NEXT: vsetivli zero, 0, e32, m1, tu, mu
378+
; RV64-NEXT: vsetivli zero, 0, e8, m1, tu, mu
379379
; RV64-NEXT: vmv8r.v v8, v0
380380
; RV64-NEXT: vmv8r.v v16, v24
381381
; RV64-NEXT: call ext2
@@ -453,7 +453,7 @@ define fastcc <vscale x 32 x i32> @ret_nxv32i32_call_nxv32i32_nxv32i32_nxv32i32_
453453
; RV32-NEXT: add a1, sp, a1
454454
; RV32-NEXT: addi a1, a1, 128
455455
; RV32-NEXT: vl8r.v v8, (a1) # Unknown-size Folded Reload
456-
; RV32-NEXT: vsetivli zero, 0, e32, m1, tu, mu
456+
; RV32-NEXT: vsetivli zero, 0, e8, m1, tu, mu
457457
; RV32-NEXT: vmv8r.v v16, v0
458458
; RV32-NEXT: call ext3
459459
; RV32-NEXT: addi sp, s0, -144
@@ -526,7 +526,7 @@ define fastcc <vscale x 32 x i32> @ret_nxv32i32_call_nxv32i32_nxv32i32_nxv32i32_
526526
; RV64-NEXT: add a1, sp, a1
527527
; RV64-NEXT: addi a1, a1, 128
528528
; RV64-NEXT: vl8r.v v8, (a1) # Unknown-size Folded Reload
529-
; RV64-NEXT: vsetivli zero, 0, e32, m1, tu, mu
529+
; RV64-NEXT: vsetivli zero, 0, e8, m1, tu, mu
530530
; RV64-NEXT: vmv8r.v v16, v0
531531
; RV64-NEXT: call ext3
532532
; RV64-NEXT: addi sp, s0, -144

‎llvm/test/CodeGen/RISCV/rvv/calling-conv.ll‎

Lines changed: 4 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -103,7 +103,7 @@ define target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @caller_tuple_return(
103103
; RV32-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
104104
; RV32-NEXT: .cfi_offset ra, -4
105105
; RV32-NEXT: call callee_tuple_return
106-
; RV32-NEXT: vsetivli zero, 0, e32, m1, tu, mu
106+
; RV32-NEXT: vsetivli zero, 0, e8, m1, tu, mu
107107
; RV32-NEXT: vmv2r.v v6, v8
108108
; RV32-NEXT: vmv2r.v v8, v10
109109
; RV32-NEXT: vmv2r.v v10, v6
@@ -120,7 +120,7 @@ define target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @caller_tuple_return(
120120
; RV64-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
121121
; RV64-NEXT: .cfi_offset ra, -8
122122
; RV64-NEXT: call callee_tuple_return
123-
; RV64-NEXT: vsetivli zero, 0, e32, m1, tu, mu
123+
; RV64-NEXT: vsetivli zero, 0, e8, m1, tu, mu
124124
; RV64-NEXT: vmv2r.v v6, v8
125125
; RV64-NEXT: vmv2r.v v8, v10
126126
; RV64-NEXT: vmv2r.v v10, v6
@@ -146,7 +146,7 @@ define void @caller_tuple_argument(target("riscv.vector.tuple", <vscale x 16 x i
146146
; RV32-NEXT: .cfi_def_cfa_offset 16
147147
; RV32-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
148148
; RV32-NEXT: .cfi_offset ra, -4
149-
; RV32-NEXT: vsetivli zero, 0, e32, m1, tu, mu
149+
; RV32-NEXT: vsetivli zero, 0, e8, m1, tu, mu
150150
; RV32-NEXT: vmv2r.v v6, v8
151151
; RV32-NEXT: vmv2r.v v8, v10
152152
; RV32-NEXT: vmv2r.v v10, v6
@@ -163,7 +163,7 @@ define void @caller_tuple_argument(target("riscv.vector.tuple", <vscale x 16 x i
163163
; RV64-NEXT: .cfi_def_cfa_offset 16
164164
; RV64-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
165165
; RV64-NEXT: .cfi_offset ra, -8
166-
; RV64-NEXT: vsetivli zero, 0, e32, m1, tu, mu
166+
; RV64-NEXT: vsetivli zero, 0, e8, m1, tu, mu
167167
; RV64-NEXT: vmv2r.v v6, v8
168168
; RV64-NEXT: vmv2r.v v8, v10
169169
; RV64-NEXT: vmv2r.v v10, v6

‎llvm/test/CodeGen/RISCV/rvv/ceil-vp.ll‎

Lines changed: 19 additions & 19 deletions
Original file line numberDiff line numberDiff line change
@@ -117,7 +117,7 @@ declare <vscale x 4 x bfloat> @llvm.vp.ceil.nxv4bf16(<vscale x 4 x bfloat>, <vsc
117117
define <vscale x 4 x bfloat> @vp_ceil_vv_nxv4bf16(<vscale x 4 x bfloat> %va, <vscale x 4 x i1> %m, i32 zeroext %evl) {
118118
; CHECK-LABEL: vp_ceil_vv_nxv4bf16:
119119
; CHECK: # %bb.0:
120-
; CHECK-NEXT: vsetivli zero, 0, e32, m1, tu, mu
120+
; CHECK-NEXT: vsetivli zero, 0, e8, m1, tu, mu
121121
; CHECK-NEXT: vmv1r.v v9, v0
122122
; CHECK-NEXT: vsetvli a1, zero, e16, m1, ta, ma
123123
; CHECK-NEXT: vfwcvtbf16.f.f.v v10, v8
@@ -170,7 +170,7 @@ declare <vscale x 8 x bfloat> @llvm.vp.ceil.nxv8bf16(<vscale x 8 x bfloat>, <vsc
170170
define <vscale x 8 x bfloat> @vp_ceil_vv_nxv8bf16(<vscale x 8 x bfloat> %va, <vscale x 8 x i1> %m, i32 zeroext %evl) {
171171
; CHECK-LABEL: vp_ceil_vv_nxv8bf16:
172172
; CHECK: # %bb.0:
173-
; CHECK-NEXT: vsetivli zero, 0, e32, m1, tu, mu
173+
; CHECK-NEXT: vsetivli zero, 0, e8, m1, tu, mu
174174
; CHECK-NEXT: vmv1r.v v10, v0
175175
; CHECK-NEXT: vsetvli a1, zero, e16, m2, ta, ma
176176
; CHECK-NEXT: vfwcvtbf16.f.f.v v12, v8
@@ -223,7 +223,7 @@ declare <vscale x 16 x bfloat> @llvm.vp.ceil.nxv16bf16(<vscale x 16 x bfloat>, <
223223
define <vscale x 16 x bfloat> @vp_ceil_vv_nxv16bf16(<vscale x 16 x bfloat> %va, <vscale x 16 x i1> %m, i32 zeroext %evl) {
224224
; CHECK-LABEL: vp_ceil_vv_nxv16bf16:
225225
; CHECK: # %bb.0:
226-
; CHECK-NEXT: vsetivli zero, 0, e32, m1, tu, mu
226+
; CHECK-NEXT: vsetivli zero, 0, e8, m1, tu, mu
227227
; CHECK-NEXT: vmv1r.v v12, v0
228228
; CHECK-NEXT: vsetvli a1, zero, e16, m4, ta, ma
229229
; CHECK-NEXT: vfwcvtbf16.f.f.v v16, v8
@@ -282,7 +282,7 @@ define <vscale x 32 x bfloat> @vp_ceil_vv_nxv32bf16(<vscale x 32 x bfloat> %va,
282282
; CHECK-NEXT: slli a1, a1, 3
283283
; CHECK-NEXT: sub sp, sp, a1
284284
; CHECK-NEXT: .cfi_escape 0x0f, 0x0d, 0x72, 0x00, 0x11, 0x10, 0x22, 0x11, 0x08, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 16 + 8 * vlenb
285-
; CHECK-NEXT: vsetivli zero, 0, e32, m1, tu, mu
285+
; CHECK-NEXT: vsetivli zero, 0, e8, m1, tu, mu
286286
; CHECK-NEXT: vmv1r.v v7, v0
287287
; CHECK-NEXT: csrr a2, vlenb
288288
; CHECK-NEXT: vsetvli a1, zero, e16, m4, ta, ma
@@ -586,7 +586,7 @@ define <vscale x 4 x half> @vp_ceil_vv_nxv4f16(<vscale x 4 x half> %va, <vscale
586586
;
587587
; ZVFHMIN-LABEL: vp_ceil_vv_nxv4f16:
588588
; ZVFHMIN: # %bb.0:
589-
; ZVFHMIN-NEXT: vsetivli zero, 0, e32, m1, tu, mu
589+
; ZVFHMIN-NEXT: vsetivli zero, 0, e8, m1, tu, mu
590590
; ZVFHMIN-NEXT: vmv1r.v v9, v0
591591
; ZVFHMIN-NEXT: vsetvli a1, zero, e16, m1, ta, ma
592592
; ZVFHMIN-NEXT: vfwcvt.f.f.v v10, v8
@@ -654,7 +654,7 @@ declare <vscale x 8 x half> @llvm.vp.ceil.nxv8f16(<vscale x 8 x half>, <vscale x
654654
define <vscale x 8 x half> @vp_ceil_vv_nxv8f16(<vscale x 8 x half> %va, <vscale x 8 x i1> %m, i32 zeroext %evl) {
655655
; ZVFH-LABEL: vp_ceil_vv_nxv8f16:
656656
; ZVFH: # %bb.0:
657-
; ZVFH-NEXT: vsetivli zero, 0, e32, m1, tu, mu
657+
; ZVFH-NEXT: vsetivli zero, 0, e8, m1, tu, mu
658658
; ZVFH-NEXT: vmv1r.v v10, v0
659659
; ZVFH-NEXT: lui a1, %hi(.LCPI18_0)
660660
; ZVFH-NEXT: flh fa5, %lo(.LCPI18_0)(a1)
@@ -674,7 +674,7 @@ define <vscale x 8 x half> @vp_ceil_vv_nxv8f16(<vscale x 8 x half> %va, <vscale
674674
;
675675
; ZVFHMIN-LABEL: vp_ceil_vv_nxv8f16:
676676
; ZVFHMIN: # %bb.0:
677-
; ZVFHMIN-NEXT: vsetivli zero, 0, e32, m1, tu, mu
677+
; ZVFHMIN-NEXT: vsetivli zero, 0, e8, m1, tu, mu
678678
; ZVFHMIN-NEXT: vmv1r.v v10, v0
679679
; ZVFHMIN-NEXT: vsetvli a1, zero, e16, m2, ta, ma
680680
; ZVFHMIN-NEXT: vfwcvt.f.f.v v12, v8
@@ -742,7 +742,7 @@ declare <vscale x 16 x half> @llvm.vp.ceil.nxv16f16(<vscale x 16 x half>, <vscal
742742
define <vscale x 16 x half> @vp_ceil_vv_nxv16f16(<vscale x 16 x half> %va, <vscale x 16 x i1> %m, i32 zeroext %evl) {
743743
; ZVFH-LABEL: vp_ceil_vv_nxv16f16:
744744
; ZVFH: # %bb.0:
745-
; ZVFH-NEXT: vsetivli zero, 0, e32, m1, tu, mu
745+
; ZVFH-NEXT: vsetivli zero, 0, e8, m1, tu, mu
746746
; ZVFH-NEXT: vmv1r.v v12, v0
747747
; ZVFH-NEXT: lui a1, %hi(.LCPI20_0)
748748
; ZVFH-NEXT: flh fa5, %lo(.LCPI20_0)(a1)
@@ -762,7 +762,7 @@ define <vscale x 16 x half> @vp_ceil_vv_nxv16f16(<vscale x 16 x half> %va, <vsca
762762
;
763763
; ZVFHMIN-LABEL: vp_ceil_vv_nxv16f16:
764764
; ZVFHMIN: # %bb.0:
765-
; ZVFHMIN-NEXT: vsetivli zero, 0, e32, m1, tu, mu
765+
; ZVFHMIN-NEXT: vsetivli zero, 0, e8, m1, tu, mu
766766
; ZVFHMIN-NEXT: vmv1r.v v12, v0
767767
; ZVFHMIN-NEXT: vsetvli a1, zero, e16, m4, ta, ma
768768
; ZVFHMIN-NEXT: vfwcvt.f.f.v v16, v8
@@ -830,7 +830,7 @@ declare <vscale x 32 x half> @llvm.vp.ceil.nxv32f16(<vscale x 32 x half>, <vscal
830830
define <vscale x 32 x half> @vp_ceil_vv_nxv32f16(<vscale x 32 x half> %va, <vscale x 32 x i1> %m, i32 zeroext %evl) {
831831
; ZVFH-LABEL: vp_ceil_vv_nxv32f16:
832832
; ZVFH: # %bb.0:
833-
; ZVFH-NEXT: vsetivli zero, 0, e32, m1, tu, mu
833+
; ZVFH-NEXT: vsetivli zero, 0, e8, m1, tu, mu
834834
; ZVFH-NEXT: vmv1r.v v16, v0
835835
; ZVFH-NEXT: lui a1, %hi(.LCPI22_0)
836836
; ZVFH-NEXT: flh fa5, %lo(.LCPI22_0)(a1)
@@ -856,7 +856,7 @@ define <vscale x 32 x half> @vp_ceil_vv_nxv32f16(<vscale x 32 x half> %va, <vsca
856856
; ZVFHMIN-NEXT: slli a1, a1, 3
857857
; ZVFHMIN-NEXT: sub sp, sp, a1
858858
; ZVFHMIN-NEXT: .cfi_escape 0x0f, 0x0d, 0x72, 0x00, 0x11, 0x10, 0x22, 0x11, 0x08, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 16 + 8 * vlenb
859-
; ZVFHMIN-NEXT: vsetivli zero, 0, e32, m1, tu, mu
859+
; ZVFHMIN-NEXT: vsetivli zero, 0, e8, m1, tu, mu
860860
; ZVFHMIN-NEXT: vmv1r.v v7, v0
861861
; ZVFHMIN-NEXT: csrr a2, vlenb
862862
; ZVFHMIN-NEXT: vsetvli a1, zero, e16, m4, ta, ma
@@ -1079,7 +1079,7 @@ declare <vscale x 4 x float> @llvm.vp.ceil.nxv4f32(<vscale x 4 x float>, <vscale
10791079
define <vscale x 4 x float> @vp_ceil_vv_nxv4f32(<vscale x 4 x float> %va, <vscale x 4 x i1> %m, i32 zeroext %evl) {
10801080
; CHECK-LABEL: vp_ceil_vv_nxv4f32:
10811081
; CHECK: # %bb.0:
1082-
; CHECK-NEXT: vsetivli zero, 0, e32, m1, tu, mu
1082+
; CHECK-NEXT: vsetivli zero, 0, e8, m1, tu, mu
10831083
; CHECK-NEXT: vmv1r.v v10, v0
10841084
; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, ma
10851085
; CHECK-NEXT: vfabs.v v12, v8, v0.t
@@ -1124,7 +1124,7 @@ declare <vscale x 8 x float> @llvm.vp.ceil.nxv8f32(<vscale x 8 x float>, <vscale
11241124
define <vscale x 8 x float> @vp_ceil_vv_nxv8f32(<vscale x 8 x float> %va, <vscale x 8 x i1> %m, i32 zeroext %evl) {
11251125
; CHECK-LABEL: vp_ceil_vv_nxv8f32:
11261126
; CHECK: # %bb.0:
1127-
; CHECK-NEXT: vsetivli zero, 0, e32, m1, tu, mu
1127+
; CHECK-NEXT: vsetivli zero, 0, e8, m1, tu, mu
11281128
; CHECK-NEXT: vmv1r.v v12, v0
11291129
; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, ma
11301130
; CHECK-NEXT: vfabs.v v16, v8, v0.t
@@ -1169,7 +1169,7 @@ declare <vscale x 16 x float> @llvm.vp.ceil.nxv16f32(<vscale x 16 x float>, <vsc
11691169
define <vscale x 16 x float> @vp_ceil_vv_nxv16f32(<vscale x 16 x float> %va, <vscale x 16 x i1> %m, i32 zeroext %evl) {
11701170
; CHECK-LABEL: vp_ceil_vv_nxv16f32:
11711171
; CHECK: # %bb.0:
1172-
; CHECK-NEXT: vsetivli zero, 0, e32, m1, tu, mu
1172+
; CHECK-NEXT: vsetivli zero, 0, e8, m1, tu, mu
11731173
; CHECK-NEXT: vmv1r.v v16, v0
11741174
; CHECK-NEXT: vsetvli zero, a0, e32, m8, ta, ma
11751175
; CHECK-NEXT: vfabs.v v24, v8, v0.t
@@ -1256,7 +1256,7 @@ declare <vscale x 2 x double> @llvm.vp.ceil.nxv2f64(<vscale x 2 x double>, <vsca
12561256
define <vscale x 2 x double> @vp_ceil_vv_nxv2f64(<vscale x 2 x double> %va, <vscale x 2 x i1> %m, i32 zeroext %evl) {
12571257
; CHECK-LABEL: vp_ceil_vv_nxv2f64:
12581258
; CHECK: # %bb.0:
1259-
; CHECK-NEXT: vsetivli zero, 0, e32, m1, tu, mu
1259+
; CHECK-NEXT: vsetivli zero, 0, e8, m1, tu, mu
12601260
; CHECK-NEXT: vmv1r.v v10, v0
12611261
; CHECK-NEXT: lui a1, %hi(.LCPI36_0)
12621262
; CHECK-NEXT: fld fa5, %lo(.LCPI36_0)(a1)
@@ -1301,7 +1301,7 @@ declare <vscale x 4 x double> @llvm.vp.ceil.nxv4f64(<vscale x 4 x double>, <vsca
13011301
define <vscale x 4 x double> @vp_ceil_vv_nxv4f64(<vscale x 4 x double> %va, <vscale x 4 x i1> %m, i32 zeroext %evl) {
13021302
; CHECK-LABEL: vp_ceil_vv_nxv4f64:
13031303
; CHECK: # %bb.0:
1304-
; CHECK-NEXT: vsetivli zero, 0, e32, m1, tu, mu
1304+
; CHECK-NEXT: vsetivli zero, 0, e8, m1, tu, mu
13051305
; CHECK-NEXT: vmv1r.v v12, v0
13061306
; CHECK-NEXT: lui a1, %hi(.LCPI38_0)
13071307
; CHECK-NEXT: fld fa5, %lo(.LCPI38_0)(a1)
@@ -1346,7 +1346,7 @@ declare <vscale x 7 x double> @llvm.vp.ceil.nxv7f64(<vscale x 7 x double>, <vsca
13461346
define <vscale x 7 x double> @vp_ceil_vv_nxv7f64(<vscale x 7 x double> %va, <vscale x 7 x i1> %m, i32 zeroext %evl) {
13471347
; CHECK-LABEL: vp_ceil_vv_nxv7f64:
13481348
; CHECK: # %bb.0:
1349-
; CHECK-NEXT: vsetivli zero, 0, e32, m1, tu, mu
1349+
; CHECK-NEXT: vsetivli zero, 0, e8, m1, tu, mu
13501350
; CHECK-NEXT: vmv1r.v v16, v0
13511351
; CHECK-NEXT: lui a1, %hi(.LCPI40_0)
13521352
; CHECK-NEXT: fld fa5, %lo(.LCPI40_0)(a1)
@@ -1391,7 +1391,7 @@ declare <vscale x 8 x double> @llvm.vp.ceil.nxv8f64(<vscale x 8 x double>, <vsca
13911391
define <vscale x 8 x double> @vp_ceil_vv_nxv8f64(<vscale x 8 x double> %va, <vscale x 8 x i1> %m, i32 zeroext %evl) {
13921392
; CHECK-LABEL: vp_ceil_vv_nxv8f64:
13931393
; CHECK: # %bb.0:
1394-
; CHECK-NEXT: vsetivli zero, 0, e32, m1, tu, mu
1394+
; CHECK-NEXT: vsetivli zero, 0, e8, m1, tu, mu
13951395
; CHECK-NEXT: vmv1r.v v16, v0
13961396
; CHECK-NEXT: lui a1, %hi(.LCPI42_0)
13971397
; CHECK-NEXT: fld fa5, %lo(.LCPI42_0)(a1)
@@ -1443,7 +1443,7 @@ define <vscale x 16 x double> @vp_ceil_vv_nxv16f64(<vscale x 16 x double> %va, <
14431443
; CHECK-NEXT: slli a1, a1, 3
14441444
; CHECK-NEXT: sub sp, sp, a1
14451445
; CHECK-NEXT: .cfi_escape 0x0f, 0x0d, 0x72, 0x00, 0x11, 0x10, 0x22, 0x11, 0x08, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 16 + 8 * vlenb
1446-
; CHECK-NEXT: vsetivli zero, 0, e32, m1, tu, mu
1446+
; CHECK-NEXT: vsetivli zero, 0, e8, m1, tu, mu
14471447
; CHECK-NEXT: vmv1r.v v7, v0
14481448
; CHECK-NEXT: csrr a1, vlenb
14491449
; CHECK-NEXT: lui a2, %hi(.LCPI44_0)

‎llvm/test/CodeGen/RISCV/rvv/compressstore.ll‎

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -197,7 +197,7 @@ entry:
197197
define void @test_compresstore_v256i8(ptr %p, <256 x i1> %mask, <256 x i8> %data) {
198198
; RV64-LABEL: test_compresstore_v256i8:
199199
; RV64: # %bb.0: # %entry
200-
; RV64-NEXT: vsetivli zero, 0, e32, m1, tu, mu
200+
; RV64-NEXT: vsetivli zero, 0, e8, m1, tu, mu
201201
; RV64-NEXT: vmv1r.v v7, v8
202202
; RV64-NEXT: li a2, 128
203203
; RV64-NEXT: vsetivli zero, 1, e64, m1, ta, ma
@@ -231,7 +231,7 @@ define void @test_compresstore_v256i8(ptr %p, <256 x i1> %mask, <256 x i8> %data
231231
; RV32-NEXT: slli a2, a2, 3
232232
; RV32-NEXT: sub sp, sp, a2
233233
; RV32-NEXT: .cfi_escape 0x0f, 0x0d, 0x72, 0x00, 0x11, 0x10, 0x22, 0x11, 0x08, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 16 + 8 * vlenb
234-
; RV32-NEXT: vsetivli zero, 0, e32, m1, tu, mu
234+
; RV32-NEXT: vsetivli zero, 0, e8, m1, tu, mu
235235
; RV32-NEXT: vmv8r.v v24, v16
236236
; RV32-NEXT: li a2, 128
237237
; RV32-NEXT: vsetivli zero, 1, e64, m1, ta, ma

‎llvm/test/CodeGen/RISCV/rvv/constant-folding-crash.ll‎

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -18,7 +18,7 @@
1818
define void @constant_folding_crash(ptr %v54, <4 x ptr> %lanes.a, <4 x ptr> %lanes.b, <4 x i1> %sel) {
1919
; RV32-LABEL: constant_folding_crash:
2020
; RV32: # %bb.0: # %entry
21-
; RV32-NEXT: vsetivli zero, 0, e32, m1, tu, mu
21+
; RV32-NEXT: vsetivli zero, 0, e8, m1, tu, mu
2222
; RV32-NEXT: vmv1r.v v10, v0
2323
; RV32-NEXT: lw a0, 8(a0)
2424
; RV32-NEXT: andi a0, a0, 1
@@ -44,7 +44,7 @@ define void @constant_folding_crash(ptr %v54, <4 x ptr> %lanes.a, <4 x ptr> %lan
4444
;
4545
; RV64-LABEL: constant_folding_crash:
4646
; RV64: # %bb.0: # %entry
47-
; RV64-NEXT: vsetivli zero, 0, e32, m1, tu, mu
47+
; RV64-NEXT: vsetivli zero, 0, e8, m1, tu, mu
4848
; RV64-NEXT: vmv1r.v v12, v0
4949
; RV64-NEXT: ld a0, 8(a0)
5050
; RV64-NEXT: andi a0, a0, 1

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