[AMDGPU] Update lit test.

Author: harrisonGPU

llvm/test/CodeGen/AMDGPU/fold-freeze-fmul-to-fma.ll

@@ -7,9 +7,9 @@ define float @fma_from_freeze_mul_add_left(float %x, float %y) {
 ; CHECK-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
 ; CHECK-NEXT:    v_fma_f32 v0, v0, v1, 1.0
 ; CHECK-NEXT:    s_setpc_b64 s[30:31]
-  %mul = fmul reassoc nsz arcp contract afn float %x, %y
+  %mul = fmul contract float %x, %y
   %mul.fr = freeze float %mul
-  %add = fadd reassoc nsz arcp contract afn float %mul.fr, 1.000000e+00
+  %add = fadd contract float %mul.fr, 1.000000e+00
   ret float %add
 }
 
@@ -21,9 +21,9 @@ define float @fma_from_freeze_mul_add_left_with_nnan(float %x, float %y) {
 ; CHECK-NEXT:    s_delay_alu instid0(VALU_DEP_1)
 ; CHECK-NEXT:    v_add_f32_e32 v0, 1.0, v0
 ; CHECK-NEXT:    s_setpc_b64 s[30:31]
-  %mul = fmul reassoc nnan nsz arcp contract afn float %x, %y
+  %mul = fmul nnan contract afn float %x, %y
   %mul.fr = freeze float %mul
-  %add = fadd reassoc nnan nsz arcp contract afn float %mul.fr, 1.000000e+00
+  %add = fadd nnan contract float %mul.fr, 1.000000e+00
   ret float %add
 }
 
@@ -33,9 +33,9 @@ define float @fma_from_freeze_mul_add_right(float %x, float %y) {
 ; CHECK-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
 ; CHECK-NEXT:    v_fma_f32 v0, v0, v1, 1.0
 ; CHECK-NEXT:    s_setpc_b64 s[30:31]
-  %mul = fmul reassoc nsz arcp contract afn float %x, %y
+  %mul = fmul contract float %x, %y
   %mul.fr = freeze float %mul
-  %add = fadd reassoc nsz arcp contract afn float 1.000000e+00, %mul.fr
+  %add = fadd contract float 1.000000e+00, %mul.fr
   ret float %add
 }
 
@@ -47,9 +47,9 @@ define float @fma_from_freeze_mul_add_right_with_nnan(float %x, float %y) {
 ; CHECK-NEXT:    s_delay_alu instid0(VALU_DEP_1)
 ; CHECK-NEXT:    v_add_f32_e32 v0, 1.0, v0
 ; CHECK-NEXT:    s_setpc_b64 s[30:31]
-  %mul = fmul reassoc nnan nsz arcp contract afn float %x, %y
+  %mul = fmul nnan contract float %x, %y
   %mul.fr = freeze float %mul
-  %add = fadd reassoc nnan nsz arcp contract afn float 1.000000e+00, %mul.fr
+  %add = fadd nnan contract float 1.000000e+00, %mul.fr
   ret float %add
 }
 
@@ -59,9 +59,9 @@ define float @fma_from_freeze_mul_sub_left(float %x, float %y) {
 ; CHECK-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
 ; CHECK-NEXT:    v_fma_f32 v0, v0, v1, -1.0
 ; CHECK-NEXT:    s_setpc_b64 s[30:31]
-  %mul = fmul reassoc nsz arcp contract afn float %x, %y
+  %mul = fmul contract float %x, %y
   %mul.fr = freeze float %mul
-  %sub = fsub reassoc nsz arcp contract afn float %mul.fr, 1.000000e+00
+  %sub = fsub contract float %mul.fr, 1.000000e+00
   ret float %sub
 }
 
@@ -73,9 +73,9 @@ define float @fma_from_freeze_mul_sub_left_with_nnan(float %x, float %y) {
 ; CHECK-NEXT:    s_delay_alu instid0(VALU_DEP_1)
 ; CHECK-NEXT:    v_add_f32_e32 v0, -1.0, v0
 ; CHECK-NEXT:    s_setpc_b64 s[30:31]
-  %mul = fmul reassoc nnan nsz arcp contract afn float %x, %y
+  %mul = fmul nnan contract float %x, %y
   %mul.fr = freeze float %mul
-  %sub = fsub reassoc nnan nsz arcp contract afn float %mul.fr, 1.000000e+00
+  %sub = fsub nnan contract float %mul.fr, 1.000000e+00
   ret float %sub
 }
 
@@ -85,9 +85,9 @@ define float @fma_from_freeze_mul_sub_right(float %x, float %y) {
 ; CHECK-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
 ; CHECK-NEXT:    v_fma_f32 v0, -v0, v1, 1.0
 ; CHECK-NEXT:    s_setpc_b64 s[30:31]
-  %mul = fmul reassoc nsz arcp contract afn float %x, %y
+  %mul = fmul contract float %x, %y
   %mul.fr = freeze float %mul
-  %sub = fsub reassoc nsz arcp contract afn float 1.000000e+00, %mul.fr
+  %sub = fsub contract float 1.000000e+00, %mul.fr
   ret float %sub
 }
 
@@ -99,8 +99,8 @@ define float @fma_from_freeze_mul_sub_right_with_nnan(float %x, float %y) {
 ; CHECK-NEXT:    s_delay_alu instid0(VALU_DEP_1)
 ; CHECK-NEXT:    v_sub_f32_e32 v0, 1.0, v0
 ; CHECK-NEXT:    s_setpc_b64 s[30:31]
-  %mul = fmul reassoc nnan nsz arcp contract afn float %x, %y
+  %mul = fmul nnan contract float %x, %y
   %mul.fr = freeze float %mul
-  %sub = fsub reassoc nnan nsz arcp contract afn float 1.000000e+00, %mul.fr
+  %sub = fsub nnan contract float 1.000000e+00, %mul.fr
   ret float %sub
 }