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Reland [VPlan] Expand WidenInt inductions with nuw/nsw
Changes: The previous patch had to be reverted to a mismatching-OpType assert in cse. The reduced-test has now been added corresponding to a RVV pointer-induction, and the pointer-induction case has been updated to use createOverflowingBinaryOp. While at it, record VPIRFlags in VPWidenInductionRecipe.
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+47
-9
lines changed

3 files changed

+47
-9
lines changed

llvm/lib/Transforms/Vectorize/LoopVectorizationPlanner.h

Lines changed: 4 additions & 5 deletions
Original file line numberDiff line numberDiff line change
@@ -178,11 +178,10 @@ class VPBuilder {
178178
new VPInstructionWithType(Opcode, Operands, ResultTy, Flags, DL, Name));
179179
}
180180

181-
VPInstruction *createOverflowingOp(unsigned Opcode,
182-
ArrayRef<VPValue *> Operands,
183-
VPRecipeWithIRFlags::WrapFlagsTy WrapFlags,
184-
DebugLoc DL = DebugLoc::getUnknown(),
185-
const Twine &Name = "") {
181+
VPInstruction *createOverflowingOp(
182+
unsigned Opcode, ArrayRef<VPValue *> Operands,
183+
VPRecipeWithIRFlags::WrapFlagsTy WrapFlags = {false, false},
184+
DebugLoc DL = DebugLoc::getUnknown(), const Twine &Name = "") {
186185
return tryInsertInstruction(
187186
new VPInstruction(Opcode, Operands, WrapFlags, {}, DL, Name));
188187
}

llvm/lib/Transforms/Vectorize/VPlanTransforms.cpp

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -3413,7 +3413,7 @@ static void expandVPWidenPointerInduction(VPWidenPointerInductionRecipe *R,
34133413
Builder.setInsertPoint(R->getParent(), R->getParent()->getFirstNonPhi());
34143414
Type *StepTy = TypeInfo.inferScalarType(Step);
34153415
VPValue *Offset = Builder.createNaryOp(VPInstruction::StepVector, {}, StepTy);
3416-
Offset = Builder.createNaryOp(Instruction::Mul, {Offset, Step});
3416+
Offset = Builder.createOverflowingOp(Instruction::Mul, {Offset, Step});
34173417
VPValue *PtrAdd = Builder.createNaryOp(
34183418
VPInstruction::WidePtrAdd, {ScalarPtrPhi, Offset}, DL, "vector.gep");
34193419
R->replaceAllUsesWith(PtrAdd);
@@ -3423,7 +3423,7 @@ static void expandVPWidenPointerInduction(VPWidenPointerInductionRecipe *R,
34233423
Builder.setInsertPoint(ExitingBB, ExitingBB->getTerminator()->getIterator());
34243424
VF = Builder.createScalarZExtOrTrunc(VF, StepTy, TypeInfo.inferScalarType(VF),
34253425
DL);
3426-
VPValue *Inc = Builder.createNaryOp(Instruction::Mul, {Step, VF});
3426+
VPValue *Inc = Builder.createOverflowingOp(Instruction::Mul, {Step, VF});
34273427

34283428
VPValue *InductionGEP =
34293429
Builder.createPtrAdd(ScalarPtrPhi, Inc, DL, "ptr.ind");

llvm/test/Transforms/LoopVectorize/RISCV/pointer-induction.ll

Lines changed: 41 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -1,9 +1,48 @@
1-
; REQUIRES: asserts
2-
; RUN: not --crash opt -p loop-vectorize -S %s
1+
; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --check-globals none --version 6
2+
; RUN: opt -p loop-vectorize -S %s | FileCheck %s
33

44
target triple = "riscv64-unknown-linux-gnu"
55

66
define void @ptr_induction(ptr %p, ptr noalias %q, ptr noalias %p.end) #0 {
7+
; CHECK-LABEL: define void @ptr_induction(
8+
; CHECK-SAME: ptr [[P:%.*]], ptr noalias [[Q:%.*]], ptr noalias [[P_END:%.*]]) #[[ATTR0:[0-9]+]] {
9+
; CHECK-NEXT: [[ENTRY:.*:]]
10+
; CHECK-NEXT: [[P2:%.*]] = ptrtoint ptr [[P]] to i64
11+
; CHECK-NEXT: [[P_END1:%.*]] = ptrtoint ptr [[P_END]] to i64
12+
; CHECK-NEXT: [[TMP0:%.*]] = add i64 [[P_END1]], 1
13+
; CHECK-NEXT: [[TMP1:%.*]] = sub i64 [[TMP0]], [[P2]]
14+
; CHECK-NEXT: br label %[[VECTOR_PH:.*]]
15+
; CHECK: [[VECTOR_PH]]:
16+
; CHECK-NEXT: [[BROADCAST_SPLATINSERT:%.*]] = insertelement <vscale x 2 x ptr> poison, ptr [[Q]], i64 0
17+
; CHECK-NEXT: [[BROADCAST_SPLAT:%.*]] = shufflevector <vscale x 2 x ptr> [[BROADCAST_SPLATINSERT]], <vscale x 2 x ptr> poison, <vscale x 2 x i32> zeroinitializer
18+
; CHECK-NEXT: [[BROADCAST_SPLATINSERT3:%.*]] = insertelement <vscale x 2 x ptr> poison, ptr [[P]], i64 0
19+
; CHECK-NEXT: [[BROADCAST_SPLAT4:%.*]] = shufflevector <vscale x 2 x ptr> [[BROADCAST_SPLATINSERT3]], <vscale x 2 x ptr> poison, <vscale x 2 x i32> zeroinitializer
20+
; CHECK-NEXT: [[TMP2:%.*]] = call <vscale x 2 x i64> @llvm.stepvector.nxv2i64()
21+
; CHECK-NEXT: [[TMP3:%.*]] = mul <vscale x 2 x i64> [[TMP2]], splat (i64 1)
22+
; CHECK-NEXT: [[INDUCTION:%.*]] = add <vscale x 2 x i64> zeroinitializer, [[TMP3]]
23+
; CHECK-NEXT: br label %[[VECTOR_BODY:.*]]
24+
; CHECK: [[VECTOR_BODY]]:
25+
; CHECK-NEXT: [[VEC_IND:%.*]] = phi <vscale x 2 x i64> [ [[INDUCTION]], %[[VECTOR_PH]] ], [ [[VEC_IND_NEXT:%.*]], %[[VECTOR_BODY]] ]
26+
; CHECK-NEXT: [[POINTER_PHI:%.*]] = phi ptr [ [[P]], %[[VECTOR_PH]] ], [ [[PTR_IND7:%.*]], %[[VECTOR_BODY]] ]
27+
; CHECK-NEXT: [[AVL:%.*]] = phi i64 [ [[TMP1]], %[[VECTOR_PH]] ], [ [[AVL_NEXT:%.*]], %[[VECTOR_BODY]] ]
28+
; CHECK-NEXT: [[VECTOR_GEP:%.*]] = getelementptr i8, ptr [[POINTER_PHI]], <vscale x 2 x i64> [[TMP2]]
29+
; CHECK-NEXT: [[TMP4:%.*]] = call i32 @llvm.experimental.get.vector.length.i64(i64 [[AVL]], i32 2, i1 true)
30+
; CHECK-NEXT: [[TMP5:%.*]] = zext i32 [[TMP4]] to i64
31+
; CHECK-NEXT: [[BROADCAST_SPLATINSERT5:%.*]] = insertelement <vscale x 2 x i64> poison, i64 [[TMP5]], i64 0
32+
; CHECK-NEXT: [[BROADCAST_SPLAT6:%.*]] = shufflevector <vscale x 2 x i64> [[BROADCAST_SPLATINSERT5]], <vscale x 2 x i64> poison, <vscale x 2 x i32> zeroinitializer
33+
; CHECK-NEXT: [[TMP6:%.*]] = ptrtoint <vscale x 2 x ptr> [[VECTOR_GEP]] to <vscale x 2 x i64>
34+
; CHECK-NEXT: call void @llvm.vp.scatter.nxv2i64.nxv2p0(<vscale x 2 x i64> [[TMP6]], <vscale x 2 x ptr> align 8 [[BROADCAST_SPLAT]], <vscale x 2 x i1> splat (i1 true), i32 [[TMP4]])
35+
; CHECK-NEXT: call void @llvm.vp.scatter.nxv2i64.nxv2p0(<vscale x 2 x i64> [[VEC_IND]], <vscale x 2 x ptr> align 8 [[BROADCAST_SPLAT4]], <vscale x 2 x i1> splat (i1 true), i32 [[TMP4]])
36+
; CHECK-NEXT: [[AVL_NEXT]] = sub nuw i64 [[AVL]], [[TMP5]]
37+
; CHECK-NEXT: [[VEC_IND_NEXT]] = add <vscale x 2 x i64> [[VEC_IND]], [[BROADCAST_SPLAT6]]
38+
; CHECK-NEXT: [[PTR_IND7]] = getelementptr i8, ptr [[POINTER_PHI]], i64 [[TMP5]]
39+
; CHECK-NEXT: [[TMP7:%.*]] = icmp eq i64 [[AVL_NEXT]], 0
40+
; CHECK-NEXT: br i1 [[TMP7]], label %[[MIDDLE_BLOCK:.*]], label %[[VECTOR_BODY]], !llvm.loop [[LOOP0:![0-9]+]]
41+
; CHECK: [[MIDDLE_BLOCK]]:
42+
; CHECK-NEXT: br label %[[EXIT:.*]]
43+
; CHECK: [[EXIT]]:
44+
; CHECK-NEXT: ret void
45+
;
746
entry:
847
br label %loop
948

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