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This commit: (1) improve .td file after resolving merge conflict
(2) replace target check with a prediate (3) add negative tests.
1 parent 87b1908 commit 9e8d903

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5 files changed

+132
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‎llvm/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp‎

Lines changed: 6 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -1585,6 +1585,11 @@ class AMDGPUAsmParser : public MCTargetAsmParser {
15851585

15861586
bool hasKernargPreload() const { return AMDGPU::hasKernargPreload(getSTI()); }
15871587

1588+
bool isFlatInstAndNVAllowed(const MCInst &Inst) const {
1589+
uint64_t TSFlags = MII.get(Inst.getOpcode()).TSFlags;
1590+
return (TSFlags & SIInstrFlags::FLAT) && isGFX9() && !isGFX90A();
1591+
}
1592+
15881593
AMDGPUTargetStreamer &getTargetStreamer() {
15891594
MCTargetStreamer &TS = *getParser().getStreamer().getTargetStreamer();
15901595
return static_cast<AMDGPUTargetStreamer &>(TS);
@@ -5295,8 +5300,7 @@ bool AMDGPUAsmParser::validateCoherencyBits(const MCInst &Inst,
52955300
S = SMLoc::getFromPointer(&CStr.data()[CStr.find("scale_offset")]);
52965301
Error(S, "scale_offset is not supported on this GPU");
52975302
}
5298-
if ((CPol & CPol::NV) && (!isGFX9() || isGFX90A())) {
5299-
// nv not supported on GFX90A+
5303+
if ((CPol & CPol::NV) && !isFlatInstAndNVAllowed(Inst)) {
53005304
SMLoc S = getImmLoc(AMDGPUOperand::ImmTyCPol, Operands);
53015305
StringRef CStr(S.getPointer());
53025306
S = SMLoc::getFromPointer(&CStr.data()[CStr.find("nv")]);

‎llvm/lib/Target/AMDGPU/FLATInstructions.td‎

Lines changed: 29 additions & 23 deletions
Original file line numberDiff line numberDiff line change
@@ -2581,6 +2581,11 @@ class FLAT_Real_vi <bits<7> op, FLAT_Pseudo ps, bit has_sccb = ps.has_sccb> :
25812581
!subst("$sccb", !if(has_sccb, "$sccb",""), ps.AsmOperands);
25822582
}
25832583

2584+
class FLAT_Real_vi_ex_gfx9 <bits<7> op, FLAT_Pseudo ps, bit has_sccb = ps.has_sccb> :
2585+
FLAT_Real_vi <op, ps, has_sccb> {
2586+
let AssemblerPredicate = isGFX8orGFX9After908;
2587+
}
2588+
25842589
class FLAT_Real_gfx9 <bits<7> op, FLAT_Pseudo ps, bit has_sccb = ps.has_sccb> :
25852590
FLAT_Real_vi <op, ps, has_sccb> {
25862591
let AssemblerPredicate = isGFX9NotGFX90A;
@@ -2590,9 +2595,7 @@ class FLAT_Real_gfx9 <bits<7> op, FLAT_Pseudo ps, bit has_sccb = ps.has_sccb> :
25902595
}
25912596

25922597
multiclass FLAT_Real_mc_vi <bits<7> op, FLAT_Pseudo ps, bit has_sccb = ps.has_sccb> {
2593-
let AssemblerPredicate = isGFX8orGFX9After908 in { // GFX8 or GFX9's starting with 90A
2594-
def _vi: FLAT_Real_vi<op, ps, has_sccb>;
2595-
}
2598+
def _vi: FLAT_Real_vi_ex_gfx9<op, ps, has_sccb>;
25962599
def _gfx9: FLAT_Real_gfx9<op, ps, has_sccb>;
25972600
}
25982601

@@ -2602,10 +2605,10 @@ multiclass FLAT_Real_AllAddr_vi<bits<7> op,
26022605
defm _SADDR : FLAT_Real_mc_vi<op, !cast<FLAT_Pseudo>(NAME#"_SADDR"), has_sccb>;
26032606
}
26042607

2605-
multiclass FLAT_Real_AllAddr_vi_only<bits<7> op,
2608+
multiclass FLAT_Real_AllAddr_vi_ex_gfx9<bits<7> op,
26062609
bit has_sccb = !cast<FLAT_Pseudo>(NAME).has_sccb> {
2607-
def _vi : FLAT_Real_vi<op, !cast<FLAT_Pseudo>(NAME), has_sccb>;
2608-
def _SADDR_vi : FLAT_Real_vi<op, !cast<FLAT_Pseudo>(NAME#"_SADDR"), has_sccb>;
2610+
def _vi : FLAT_Real_vi_ex_gfx9<op, !cast<FLAT_Pseudo>(NAME), has_sccb>;
2611+
def _SADDR_vi : FLAT_Real_vi_ex_gfx9<op, !cast<FLAT_Pseudo>(NAME#"_SADDR"), has_sccb>;
26092612
}
26102613

26112614
class FLAT_Real_gfx940 <bits<7> op, FLAT_Pseudo ps> :
@@ -2684,35 +2687,38 @@ defm FLAT_LOAD_SHORT_D16_HI_vi : FLAT_Real_mc_vi <0x25, FLAT_LOAD_SHORT_D16_HI>;
26842687
multiclass FLAT_Real_Atomics_vi <bits<7> op,
26852688
bit has_sccb = !cast<FLAT_Pseudo>(NAME).has_sccb> {
26862689
defvar ps = !cast<FLAT_Pseudo>(NAME);
2687-
defm "" : FLAT_Real_mc_vi<op, !cast<FLAT_Pseudo>(ps.PseudoInstr), has_sccb>;
2690+
defm "" : FLAT_Real_mc_vi<op, !cast<FLAT_Pseudo>(ps.PseudoInstr), has_sccb>;
26882691
defm _RTN : FLAT_Real_mc_vi<op, !cast<FLAT_Pseudo>(ps.PseudoInstr # "_RTN"), has_sccb>;
2692+
def _RTN_agpr_vi : FLAT_Real_vi_ex_gfx9<op, !cast<FLAT_Pseudo>(ps.PseudoInstr # "_RTN_agpr"), has_sccb>;
26892693
}
26902694

2691-
// FLAT_Real_mc_vi contains a vi variant and a gfx9 variant. In some cases, only the vi
2692-
// variant is needed.
2693-
multiclass FLAT_Real_Atomics_vi_only <bits<7> op,
2695+
multiclass FLAT_Real_Atomics_vi_ex_gfx9 <bits<7> op,
26942696
bit has_sccb = !cast<FLAT_Pseudo>(NAME).has_sccb> {
26952697
defvar ps = !cast<FLAT_Pseudo>(NAME);
2696-
def _vi : FLAT_Real_vi<op, !cast<FLAT_Pseudo>(ps.PseudoInstr), has_sccb>;
2697-
def _RTN_vi : FLAT_Real_vi<op, !cast<FLAT_Pseudo>(ps.PseudoInstr # "_RTN"), has_sccb>;
2698-
def _RTN_agpr_vi : FLAT_Real_vi<op, !cast<FLAT_Pseudo>(ps.PseudoInstr # "_RTN_agpr"), has_sccb>;
2698+
def _vi : FLAT_Real_vi_ex_gfx9<op, !cast<FLAT_Pseudo>(ps.PseudoInstr), has_sccb>;
2699+
def _RTN_vi : FLAT_Real_vi_ex_gfx9<op, !cast<FLAT_Pseudo>(ps.PseudoInstr # "_RTN"), has_sccb>;
2700+
2701+
def _RTN_agpr_vi : FLAT_Real_vi_ex_gfx9<op, !cast<FLAT_Pseudo>(ps.PseudoInstr # "_RTN_agpr"), has_sccb>;
26992702
}
27002703

27012704
multiclass FLAT_Global_Real_Atomics_vi<bits<7> op,
27022705
bit has_sccb = !cast<FLAT_Pseudo>(NAME).has_sccb> :
27032706
FLAT_Real_AllAddr_vi<op, has_sccb> {
27042707
defm _RTN : FLAT_Real_mc_vi <op, !cast<FLAT_Pseudo>(NAME#"_RTN"), has_sccb>;
27052708
defm _SADDR_RTN : FLAT_Real_mc_vi <op, !cast<FLAT_Pseudo>(NAME#"_SADDR_RTN"), has_sccb>;
2709+
2710+
def _RTN_agpr_vi : FLAT_Real_vi_ex_gfx9 <op, !cast<FLAT_Pseudo>(NAME#"_RTN_agpr"), has_sccb>;
2711+
def _SADDR_RTN_agpr_vi : FLAT_Real_vi_ex_gfx9 <op, !cast<FLAT_Pseudo>(NAME#"_SADDR_RTN_agpr"), has_sccb>;
27062712
}
27072713

2708-
multiclass FLAT_Global_Real_Atomics_vi_only<bits<7> op,
2714+
multiclass FLAT_Global_Real_Atomics_vi_ex_gfx9<bits<7> op,
27092715
bit has_sccb = !cast<FLAT_Pseudo>(NAME).has_sccb> :
2710-
FLAT_Real_AllAddr_vi_only<op, has_sccb> {
2711-
def _RTN_vi : FLAT_Real_vi <op, !cast<FLAT_Pseudo>(NAME#"_RTN"), has_sccb>;
2712-
def _SADDR_RTN_vi : FLAT_Real_vi <op, !cast<FLAT_Pseudo>(NAME#"_SADDR_RTN"), has_sccb>;
2716+
FLAT_Real_AllAddr_vi_ex_gfx9<op, has_sccb> {
2717+
def _RTN_vi : FLAT_Real_vi_ex_gfx9 <op, !cast<FLAT_Pseudo>(NAME#"_RTN"), has_sccb>;
2718+
def _SADDR_RTN_vi : FLAT_Real_vi_ex_gfx9 <op, !cast<FLAT_Pseudo>(NAME#"_SADDR_RTN"), has_sccb>;
27132719

2714-
def _RTN_agpr_vi : FLAT_Real_vi <op, !cast<FLAT_Pseudo>(NAME#"_RTN_agpr"), has_sccb>;
2715-
def _SADDR_RTN_agpr_vi : FLAT_Real_vi <op, !cast<FLAT_Pseudo>(NAME#"_SADDR_RTN_agpr"), has_sccb>;
2720+
def _RTN_agpr_vi : FLAT_Real_vi_ex_gfx9 <op, !cast<FLAT_Pseudo>(NAME#"_RTN_agpr"), has_sccb>;
2721+
def _SADDR_RTN_agpr_vi : FLAT_Real_vi_ex_gfx9 <op, !cast<FLAT_Pseudo>(NAME#"_SADDR_RTN_agpr"), has_sccb>;
27162722
}
27172723

27182724
defm FLAT_ATOMIC_SWAP : FLAT_Real_Atomics_vi <0x40>;
@@ -2874,10 +2880,10 @@ let AssemblerPredicate = isGFX940Plus in {
28742880
defm GLOBAL_ATOMIC_ADD_F64 : FLAT_Global_Real_Atomics_gfx940<0x4f>;
28752881
defm GLOBAL_ATOMIC_MIN_F64 : FLAT_Global_Real_Atomics_gfx940<0x50>;
28762882
defm GLOBAL_ATOMIC_MAX_F64 : FLAT_Global_Real_Atomics_gfx940<0x51>;
2877-
defm FLAT_ATOMIC_ADD_F32 : FLAT_Real_Atomics_vi_only<0x4d>;
2878-
defm FLAT_ATOMIC_PK_ADD_F16 : FLAT_Real_Atomics_vi_only<0x4e>;
2879-
defm FLAT_ATOMIC_PK_ADD_BF16 : FLAT_Real_Atomics_vi_only<0x52>;
2880-
defm GLOBAL_ATOMIC_PK_ADD_BF16 : FLAT_Global_Real_Atomics_vi_only<0x52>;
2883+
defm FLAT_ATOMIC_ADD_F32 : FLAT_Real_Atomics_vi_ex_gfx9<0x4d>;
2884+
defm FLAT_ATOMIC_PK_ADD_F16 : FLAT_Real_Atomics_vi_ex_gfx9<0x4e>;
2885+
defm FLAT_ATOMIC_PK_ADD_BF16 : FLAT_Real_Atomics_vi_ex_gfx9<0x52>;
2886+
defm GLOBAL_ATOMIC_PK_ADD_BF16 : FLAT_Global_Real_Atomics_vi_ex_gfx9<0x52>;
28812887
} // End AssemblerPredicate = isGFX940Plus
28822888

28832889
//===----------------------------------------------------------------------===//

‎llvm/test/MC/AMDGPU/gfx90a_err.s‎

Lines changed: 43 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -674,3 +674,46 @@ v_dot8c_i32_i4 v0, v1, v2, v3 op_sel:[1,1] op_sel_hi:[1,0]
674674
v_dot8c_i32_i4 v0, v1, v2, v3 op_sel:[1,1] op_sel_hi:[1,1]
675675
// GFX90A: :[[@LINE-1]]:{{[0-9]+}}: error: not a valid operand.
676676

677+
// nv bit in FLAT instructions
678+
flat_load_ubyte v5, v[2:3] offset:4095 nv
679+
// GFX90A: :[[@LINE-1]]:{{[0-9]+}}: error: nv is not supported on this GPU
680+
681+
flat_load_ubyte a5, v[2:3] offset:4095 nv
682+
// GFX90A: :[[@LINE-1]]:{{[0-9]+}}: error: nv is not supported on this GPU
683+
684+
flat_store_dword v[2:3], v5 offset:4095 nv
685+
// GFX90A: :[[@LINE-1]]:{{[0-9]+}}: error: nv is not supported on this GPU
686+
687+
flat_store_dword v[2:3], a5 offset:4095 nv
688+
// GFX90A: :[[@LINE-1]]:{{[0-9]+}}: error: nv is not supported on this GPU
689+
690+
flat_atomic_add_f64 v[0:1], v[2:3] offset:4095 nv
691+
// GFX90A: :[[@LINE-1]]:{{[0-9]+}}: error: nv is not supported on this GPU
692+
693+
global_load_ubyte v5, v[2:3], off offset:-1 nv
694+
// GFX90A: :[[@LINE-1]]:{{[0-9]+}}: error: nv is not supported on this GPU
695+
696+
global_store_byte v[2:3], v5, off offset:-1 nv
697+
// GFX90A: :[[@LINE-1]]:{{[0-9]+}}: error: nv is not supported on this GPU
698+
699+
global_atomic_add v[2:3], v5, off nv
700+
// GFX90A: :[[@LINE-1]]:{{[0-9]+}}: error: nv is not supported on this GPU
701+
702+
global_atomic_swap a1, v[2:3], a2, off glc nv
703+
// GFX90A: :[[@LINE-1]]:{{[0-9]+}}: error: nv is not supported on this GPU
704+
705+
global_atomic_swap_x2 v[2:3], v[4:5], off nv
706+
// GFX90A: :[[@LINE-1]]:{{[0-9]+}}: error: nv is not supported on this GPU
707+
708+
global_atomic_swap_x2 v[2:3], a[4:5], off nv
709+
// GFX90A: :[[@LINE-1]]:{{[0-9]+}}: error: nv is not supported on this GPU
710+
711+
scratch_load_ubyte v5, off, s2 offset:-1 nv
712+
// GFX90A: :[[@LINE-1]]:{{[0-9]+}}: error: nv is not supported on this GPU
713+
714+
scratch_load_ubyte a5, off, s2 offset:-1 nv
715+
// GFX90A: :[[@LINE-1]]:{{[0-9]+}}: error: nv is not supported on this GPU
716+
717+
scratch_store_dword v2, v3, off nv
718+
// GFX90A: :[[@LINE-1]]:{{[0-9]+}}: error: nv is not supported on this GPU
719+

‎llvm/test/MC/AMDGPU/gfx90a_ldst_acc.s‎

Lines changed: 26 additions & 26 deletions
Original file line numberDiff line numberDiff line change
@@ -706,107 +706,107 @@ flat_load_short_d16_hi a5, v[2:3] offset:4095 glc
706706
flat_load_short_d16_hi a5, v[2:3] offset:4095 slc
707707

708708
// GFX90A: flat_atomic_swap a0, v[2:3], a2 offset:4095 glc ; encoding: [0xff,0x0f,0x01,0xdd,0x02,0x02,0x80,0x00]
709-
// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU
709+
// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
710710
flat_atomic_swap a0, v[2:3], a2 offset:4095 glc
711711

712712
// GFX90A: flat_atomic_cmpswap a0, v[2:3], a[2:3] offset:4095 glc ; encoding: [0xff,0x0f,0x05,0xdd,0x02,0x02,0x80,0x00]
713-
// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU
713+
// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
714714
flat_atomic_cmpswap a0, v[2:3], a[2:3] offset:4095 glc
715715

716716
// GFX90A: flat_atomic_add a0, v[2:3], a2 offset:4095 glc ; encoding: [0xff,0x0f,0x09,0xdd,0x02,0x02,0x80,0x00]
717-
// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU
717+
// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
718718
flat_atomic_add a0, v[2:3], a2 offset:4095 glc
719719

720720
// GFX90A: flat_atomic_sub a0, v[2:3], a2 offset:4095 glc ; encoding: [0xff,0x0f,0x0d,0xdd,0x02,0x02,0x80,0x00]
721-
// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU
721+
// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
722722
flat_atomic_sub a0, v[2:3], a2 offset:4095 glc
723723

724724
// GFX90A: flat_atomic_smin a0, v[2:3], a2 offset:4095 glc ; encoding: [0xff,0x0f,0x11,0xdd,0x02,0x02,0x80,0x00]
725-
// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU
725+
// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
726726
flat_atomic_smin a0, v[2:3], a2 offset:4095 glc
727727

728728
// GFX90A: flat_atomic_umin a0, v[2:3], a2 offset:4095 glc ; encoding: [0xff,0x0f,0x15,0xdd,0x02,0x02,0x80,0x00]
729-
// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU
729+
// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
730730
flat_atomic_umin a0, v[2:3], a2 offset:4095 glc
731731

732732
// GFX90A: flat_atomic_smax a0, v[2:3], a2 offset:4095 glc ; encoding: [0xff,0x0f,0x19,0xdd,0x02,0x02,0x80,0x00]
733-
// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU
733+
// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
734734
flat_atomic_smax a0, v[2:3], a2 offset:4095 glc
735735

736736
// GFX90A: flat_atomic_umax a0, v[2:3], a2 offset:4095 glc ; encoding: [0xff,0x0f,0x1d,0xdd,0x02,0x02,0x80,0x00]
737-
// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU
737+
// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
738738
flat_atomic_umax a0, v[2:3], a2 offset:4095 glc
739739

740740
// GFX90A: flat_atomic_and a0, v[2:3], a2 offset:4095 glc ; encoding: [0xff,0x0f,0x21,0xdd,0x02,0x02,0x80,0x00]
741-
// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU
741+
// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
742742
flat_atomic_and a0, v[2:3], a2 offset:4095 glc
743743

744744
// GFX90A: flat_atomic_or a0, v[2:3], a2 offset:4095 glc ; encoding: [0xff,0x0f,0x25,0xdd,0x02,0x02,0x80,0x00]
745-
// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU
745+
// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
746746
flat_atomic_or a0, v[2:3], a2 offset:4095 glc
747747

748748
// GFX90A: flat_atomic_xor a0, v[2:3], a2 offset:4095 glc ; encoding: [0xff,0x0f,0x29,0xdd,0x02,0x02,0x80,0x00]
749-
// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU
749+
// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
750750
flat_atomic_xor a0, v[2:3], a2 offset:4095 glc
751751

752752
// GFX90A: flat_atomic_inc a0, v[2:3], a2 offset:4095 glc ; encoding: [0xff,0x0f,0x2d,0xdd,0x02,0x02,0x80,0x00]
753-
// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU
753+
// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
754754
flat_atomic_inc a0, v[2:3], a2 offset:4095 glc
755755

756756
// GFX90A: flat_atomic_dec a0, v[2:3], a2 offset:4095 glc ; encoding: [0xff,0x0f,0x31,0xdd,0x02,0x02,0x80,0x00]
757-
// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU
757+
// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
758758
flat_atomic_dec a0, v[2:3], a2 offset:4095 glc
759759

760760
// GFX90A: flat_atomic_swap_x2 a[0:1], v[2:3], a[2:3] offset:4095 glc ; encoding: [0xff,0x0f,0x81,0xdd,0x02,0x02,0x80,0x00]
761-
// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU
761+
// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
762762
flat_atomic_swap_x2 a[0:1], v[2:3], a[2:3] offset:4095 glc
763763

764764
// GFX90A: flat_atomic_cmpswap_x2 a[0:1], v[2:3], a[2:5] offset:4095 glc ; encoding: [0xff,0x0f,0x85,0xdd,0x02,0x02,0x80,0x00]
765-
// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU
765+
// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
766766
flat_atomic_cmpswap_x2 a[0:1], v[2:3], a[2:5] offset:4095 glc
767767

768768
// GFX90A: flat_atomic_add_x2 a[0:1], v[2:3], a[2:3] offset:4095 glc ; encoding: [0xff,0x0f,0x89,0xdd,0x02,0x02,0x80,0x00]
769-
// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU
769+
// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
770770
flat_atomic_add_x2 a[0:1], v[2:3], a[2:3] offset:4095 glc
771771

772772
// GFX90A: flat_atomic_sub_x2 a[0:1], v[2:3], a[2:3] offset:4095 glc ; encoding: [0xff,0x0f,0x8d,0xdd,0x02,0x02,0x80,0x00]
773-
// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU
773+
// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
774774
flat_atomic_sub_x2 a[0:1], v[2:3], a[2:3] offset:4095 glc
775775

776776
// GFX90A: flat_atomic_smin_x2 a[0:1], v[2:3], a[2:3] offset:4095 glc ; encoding: [0xff,0x0f,0x91,0xdd,0x02,0x02,0x80,0x00]
777-
// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU
777+
// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
778778
flat_atomic_smin_x2 a[0:1], v[2:3], a[2:3] offset:4095 glc
779779

780780
// GFX90A: flat_atomic_umin_x2 a[0:1], v[2:3], a[2:3] offset:4095 glc ; encoding: [0xff,0x0f,0x95,0xdd,0x02,0x02,0x80,0x00]
781-
// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU
781+
// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
782782
flat_atomic_umin_x2 a[0:1], v[2:3], a[2:3] offset:4095 glc
783783

784784
// GFX90A: flat_atomic_smax_x2 a[0:1], v[2:3], a[2:3] offset:4095 glc ; encoding: [0xff,0x0f,0x99,0xdd,0x02,0x02,0x80,0x00]
785-
// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU
785+
// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
786786
flat_atomic_smax_x2 a[0:1], v[2:3], a[2:3] offset:4095 glc
787787

788788
// GFX90A: flat_atomic_umax_x2 a[0:1], v[2:3], a[2:3] offset:4095 glc ; encoding: [0xff,0x0f,0x9d,0xdd,0x02,0x02,0x80,0x00]
789-
// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU
789+
// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
790790
flat_atomic_umax_x2 a[0:1], v[2:3], a[2:3] offset:4095 glc
791791

792792
// GFX90A: flat_atomic_and_x2 a[0:1], v[2:3], a[2:3] offset:4095 glc ; encoding: [0xff,0x0f,0xa1,0xdd,0x02,0x02,0x80,0x00]
793-
// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU
793+
// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
794794
flat_atomic_and_x2 a[0:1], v[2:3], a[2:3] offset:4095 glc
795795

796796
// GFX90A: flat_atomic_or_x2 a[0:1], v[2:3], a[2:3] offset:4095 glc ; encoding: [0xff,0x0f,0xa5,0xdd,0x02,0x02,0x80,0x00]
797-
// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU
797+
// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
798798
flat_atomic_or_x2 a[0:1], v[2:3], a[2:3] offset:4095 glc
799799

800800
// GFX90A: flat_atomic_xor_x2 a[0:1], v[2:3], a[2:3] offset:4095 glc ; encoding: [0xff,0x0f,0xa9,0xdd,0x02,0x02,0x80,0x00]
801-
// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU
801+
// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
802802
flat_atomic_xor_x2 a[0:1], v[2:3], a[2:3] offset:4095 glc
803803

804804
// GFX90A: flat_atomic_inc_x2 a[0:1], v[2:3], a[2:3] offset:4095 glc ; encoding: [0xff,0x0f,0xad,0xdd,0x02,0x02,0x80,0x00]
805-
// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU
805+
// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
806806
flat_atomic_inc_x2 a[0:1], v[2:3], a[2:3] offset:4095 glc
807807

808808
// GFX90A: flat_atomic_dec_x2 a[0:1], v[2:3], a[2:3] offset:4095 glc ; encoding: [0xff,0x0f,0xb1,0xdd,0x02,0x02,0x80,0x00]
809-
// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU
809+
// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
810810
flat_atomic_dec_x2 a[0:1], v[2:3], a[2:3] offset:4095 glc
811811

812812
// GFX90A: flat_atomic_swap v[2:3], a2 offset:4095 ; encoding: [0xff,0x0f,0x00,0xdd,0x02,0x02,0x80,0x00]

‎llvm/test/MC/AMDGPU/gfx942_err.s‎

Lines changed: 28 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -125,3 +125,31 @@ global_load_dword v[2:3], off lds
125125

126126
scratch_load_dword v2, off lds
127127
// GFX942: :[[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
128+
129+
// nv bit in FLAT instructions
130+
flat_load_ubyte v5, v[2:3] offset:4095 nv
131+
// GFX942: :[[@LINE-1]]:{{[0-9]+}}: error: nv is not supported on this GPU
132+
133+
flat_store_dword v[2:3], v5 offset:4095 nv
134+
// GFX942: :[[@LINE-1]]:{{[0-9]+}}: error: nv is not supported on this GPU
135+
136+
flat_atomic_add_f32 v[2:3], v5 nv
137+
// GFX942: :[[@LINE-1]]:{{[0-9]+}}: error: nv is not supported on this GPU
138+
139+
global_load_dword v2, v[2:3], off sc0 nv
140+
// GFX942: :[[@LINE-1]]:{{[0-9]+}}: error: nv is not supported on this GPU
141+
142+
global_store_dword v[2:3], v5 off sc0 nv
143+
// GFX942: :[[@LINE-1]]:{{[0-9]+}}: error: nv is not supported on this GPU
144+
145+
global_atomic_add_f64 v[0:1], v[2:3], off sc1 nv
146+
// GFX942: :[[@LINE-1]]:{{[0-9]+}}: error: nv is not supported on this GPU
147+
148+
global_atomic_swap v0, v[2:3], v5 off sc0 nv
149+
// GFX942: :[[@LINE-1]]:{{[0-9]+}}: error: nv is not supported on this GPU
150+
151+
scratch_load_lds_dword v2, off nv
152+
// GFX942: :[[@LINE-1]]:{{[0-9]+}}: error: nv is not supported on this GPU
153+
154+
scratch_store_dword v2, v3, off nv
155+
// GFX942: :[[@LINE-1]]:{{[0-9]+}}: error: nv is not supported on this GPU

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