Updates per review.

Author: JonPsson1

compiler-rt/lib/builtins/extendhfdf2.c

@@ -10,8 +10,6 @@
 #define DST_DOUBLE
 #include "fp_extend_impl.inc"
 
-// Use a forwarding definition and noinline to implement a poor man's alias,
-// as there isn't a good cross-platform way of defining one.
 COMPILER_RT_ABI NOINLINE dst_t __extendhfdf2(src_t a) {
   return __extendXfYf2__(a);
 }

llvm/lib/Target/SystemZ/SystemZISelLowering.cpp

@@ -627,6 +627,9 @@ class SystemZTargetLowering : public TargetLowering {
                    bool IsSigned, SDLoc DL, bool DoesNotReturn,
                    bool IsReturnValueUsed) const;
 
+  SDValue useLibCall(SelectionDAG &DAG, RTLIB::Libcall LC, MVT VT, SDValue Arg,
+                     SDLoc DL, SDValue Chain, bool IsStrict) const;
+
   bool CanLowerReturn(CallingConv::ID CallConv, MachineFunction &MF,
                       bool isVarArg,
                       const SmallVectorImpl<ISD::OutputArg> &Outs,
@@ -747,9 +750,7 @@ class SystemZTargetLowering : public TargetLowering {
   SDValue lowerFSHR(SDValue Op, SelectionDAG &DAG) const;
   SDValue lowerFP_EXTEND(SDValue Op, SelectionDAG &DAG) const;
   SDValue lower_FP_TO_INT(SDValue Op, SelectionDAG &DAG) const;
-  SDValue lowerSTRICT_FP_TO_INT(SDValue Op, SelectionDAG &DAG) const;
   SDValue lower_INT_TO_FP(SDValue Op, SelectionDAG &DAG) const;
-  SDValue lowerSTRICT_INT_TO_FP(SDValue Op, SelectionDAG &DAG) const;
   SDValue lowerLoadF16(SDValue Op, SelectionDAG &DAG) const;
   SDValue lowerStoreF16(SDValue Op, SelectionDAG &DAG) const;
 

llvm/lib/Target/SystemZ/SystemZISelLowering.h

@@ -142,7 +142,7 @@ let Predicates = [FeatureVector] in {
   // LEY and LDY offer full 20-bit displacement fields.  It's often better
   // to use those instructions rather than force a 20-bit displacement
   // into a GPR temporary.
-  let mayLoad = 1, canFoldAsLoad = 1 in {
+  let mayLoad = 1, SimpleBDXLoad = 1, canFoldAsLoad = 1 in {
     def VL16 : UnaryAliasVRX<z_load, v16hb, bdxaddr12pair>;
     def VL32 : UnaryAliasVRX<z_load, v32sb, bdxaddr12pair>;
     def VL64 : UnaryAliasVRX<z_load, v64db, bdxaddr12pair>;
@@ -240,7 +240,7 @@ let Predicates = [FeatureVector] in {
   // STEY and STDY offer full 20-bit displacement fields.  It's often better
   // to use those instructions rather than force a 20-bit displacement
   // into a GPR temporary.
-  let mayStore = 1 in {
+  let mayStore = 1, SimpleBDXStore = 1 in {
     def VST16 : StoreAliasVRX<store, v16hb, bdxaddr12pair>;
     def VST32 : StoreAliasVRX<store, v32sb, bdxaddr12pair>;
     def VST64 : StoreAliasVRX<store, v64db, bdxaddr12pair>;

llvm/lib/Target/SystemZ/SystemZInstrVector.td

@@ -7,7 +7,7 @@
 define half @f1(ptr %src) {
 ; CHECK-LABEL: f1:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    lh %r0, 0(%r2)
+; CHECK-NEXT:    lgh %r0, 0(%r2)
 ; CHECK-NEXT:    sllg %r0, %r0, 48
 ; CHECK-NEXT:    ldgr %f0, %r0
 ; CHECK-NEXT:    # kill: def $f0h killed $f0h killed $f0d

llvm/test/CodeGen/SystemZ/atomic-load-10.ll

@@ -7,8 +7,9 @@
 declare half @llvm.fabs.f16(half %f)
 define half @f0(half %f) {
 ; CHECK-LABEL: f0:
-; CHECK: brasl %r14, __extendhfsf2@PLT
-; CHECK: lpdfr %f0, %f0
+; CHECK:      brasl %r14, __extendhfsf2@PLT
+; CHECK-NEXT: lpdfr %f0, %f0
+; CHECK-NEXT: brasl %r14, __truncsfhf2@PLT
 ; CHECK: br %r14
   %res = call half @llvm.fabs.f16(half %f)
   ret half %res

llvm/test/CodeGen/SystemZ/fp-abs-01.ll

@@ -6,9 +6,9 @@
 declare half @llvm.fabs.f16(half %f)
 define half @f0(half %f) {
 ; CHECK-LABEL: f0:
-; CHECK: brasl %r14, __extendhfsf2@PLT
-; CHECK: lpdfr %f0, %f0
-; CHECK: brasl %r14, __truncsfhf2@PLT
+; CHECK:      brasl %r14, __extendhfsf2@PLT
+; CHECK-NEXT: lpdfr %f0, %f0
+; CHECK-NEXT: brasl %r14, __truncsfhf2@PLT
 ; CHECK: br %r14
   %res = call half @llvm.fabs.f16(half %f)
   ret half %res

llvm/test/CodeGen/SystemZ/fp-abs-03.ll

@@ -5,7 +5,9 @@
 ; Test i64->f16. For z10, this results in just a single a libcall.
 define half @f0(i64 %i) {
 ; CHECK-LABEL: f0:
-; CHECK: brasl %r14, __floatundihf@PLT
+; CHECK: cegbr
+; CHECK: aebr
+; CHECK: brasl %r14, __truncsfhf2@PLT
 ; CHECK: br %r14
   %conv = uitofp i64 %i to half
   ret half %conv

llvm/test/CodeGen/SystemZ/fp-conv-08.ll

@@ -33,7 +33,8 @@ define float @f3(i128 %i) {
 ; Test signed i128->f16.
 define half @f4(i128 %i) {
 ; CHECK-LABEL: f4:
-; CHECK: brasl %r14, __floattihf@PLT
+; CHECK: brasl   %r14, __floattisf@PLT
+; CHECK: brasl   %r14, __truncsfhf2@PLT
 ; CHECK: br %r14
   %conv = sitofp i128 %i to half
   ret half %conv
@@ -69,7 +70,8 @@ define float @f7(i128 %i) {
 ; Test unsigned i128->f16.
 define half @f8(i128 %i) {
 ; CHECK-LABEL: f8:
-; CHECK: brasl %r14, __floatuntihf@PLT
+; CHECK: brasl   %r14, __floatuntisf@PLT
+; CHECK: brasl   %r14, __truncsfhf2@PLT
 ; CHECK: br %r14
   %conv = uitofp i128 %i to half
   ret half %conv
@@ -105,7 +107,8 @@ define i128 @f11(float %f) {
 ; Test signed f16->i128.
 define i128 @f12(half %f) {
 ; CHECK-LABEL: f12:
-; CHECK: brasl %r14, __fixhfti@PLT
+; CHECK: brasl %r14, __extendhfsf2@PLT
+; CHECK: brasl %r14, __fixsfti@PLT
 ; CHECK: br %r14
   %conv = fptosi half %f to i128
   ret i128 %conv
@@ -141,7 +144,8 @@ define i128 @f15(float %f) {
 ; Test unsigned f16->i128.
 define i128 @f16(half %f) {
 ; CHECK-LABEL: f16:
-; CHECK: brasl %r14, __fixunshfti@PLT
+; CHECK: brasl %r14, __extendhfsf2@PLT
+; CHECK: brasl %r14, __fixunssfti@PLT
 ; CHECK: br %r14
   %conv = fptoui half %f to i128
   ret i128 %conv

llvm/test/CodeGen/SystemZ/fp-conv-20.ll

@@ -2,23 +2,11 @@
 ;
 ; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s
 
-declare half @copysignh(half, half) readnone
 declare float @copysignf(float, float) readnone
 declare double @copysign(double, double) readnone
 ; FIXME: not really the correct prototype for SystemZ.
 declare fp128 @copysignl(fp128, fp128) readnone
 
-; Test f32 copies in which the sign comes from an f16.
-define float @f0(float %a, half %bh) {
-; CHECK-LABEL: f0:
-; CHECK: brasl %r14, __extendhfsf2@PLT
-; CHECK: cpsdr %f0, %f0, %f8
-; CHECK: br %r14
-  %b = fpext half %bh to float
-  %res = call float @copysignf(float %a, float %b) readnone
-  ret float %res
-}
-
 ; Test f32 copies in which the sign comes from an f32.
 define float @f1(float %a, float %b) {
 ; CHECK-LABEL: f1:
@@ -138,23 +126,3 @@ define void @f9(ptr %cptr, ptr %aptr, ptr %bptr) {
   store fp128 %c, ptr %cptr
   ret void
 }
-
-; Test f16 copies in which the sign comes from an f16.
-define half @f10(half %a, half %b) {
-; CHECK-LABEL: f10:
-; CHECK: brasl %r14, copysignh@PLT
-; CHECK: br %r14
-  %res = call half @copysignh(half %a, half %b) readnone
-  ret half %res
-}
-
-; Test f16 copies in which the sign comes from an f32.
-define half @f11(half %a, float %bf) {
-; CHECK-LABEL: f11:
-; CHECK: brasl %r14, __truncsfhf2@PLT
-; CHECK: brasl %r14, copysignh@PLT
-; CHECK: br %r14
-  %b = fptrunc float %bf to half
-  %res = call half @copysignh(half %a, half %b) readnone
-  ret half %res
-}