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4 files changed

+172
-62
lines changed

4 files changed

+172
-62
lines changed

‎llvm/lib/Target/ARM/ARMISelLowering.cpp‎

Lines changed: 51 additions & 5 deletions
Original file line numberDiff line numberDiff line change
@@ -5639,7 +5639,7 @@ SDValue ARMTargetLowering::LowerABS(SDValue Op, SelectionDAG &DAG) const {
56395639
}
56405640
SDValue Neg = DAG.getNode(ISD::SUB, DL, MVT::i32,
56415641
DAG.getConstant(0, DL, MVT::i32), Op.getOperand(0));
5642-
// Generate SUBS & CSEL.
5642+
// Generate SUBS & CMOV.
56435643
SDValue Cmp = DAG.getNode(ARMISD::CMP, DL, FlagsVT, Op.getOperand(0),
56445644
DAG.getConstant(0, DL, MVT::i32));
56455645
return DAG.getNode(ARMISD::CMOV, DL, MVT::i32, Op.getOperand(0), Neg,
@@ -5679,7 +5679,7 @@ SDValue ARMTargetLowering::LowerABD(SDValue Op, SelectionDAG &DAG) const {
56795679
}
56805680
}
56815681

5682-
// Generate SUBS and CSEL for absolute difference (like LowerABS)
5682+
// Generate SUBS and CMOV for absolute difference (like LowerABS)
56835683
// Compute a - b with flags
56845684
SDValue Cmp =
56855685
DAG.getNode(ARMISD::SUBC, DL, DAG.getVTList(MVT::i32, FlagsVT), LHS, RHS);
@@ -5688,11 +5688,12 @@ SDValue ARMTargetLowering::LowerABD(SDValue Op, SelectionDAG &DAG) const {
56885688
SDValue Neg = DAG.getNode(ISD::SUB, DL, MVT::i32,
56895689
DAG.getConstant(0, DL, MVT::i32), Cmp.getValue(0));
56905690

5691-
// For unsigned: use HS (a >= b) to select a-b, otherwise b-a
5692-
// For signed: use GE (a >= b) to select a-b, otherwise b-a
5691+
// For unsigned: use LO (a < b) to select -(a-b), which is the same as b-a in
5692+
// twos complement, otherwise a-b For signed: use MI (a - b < 0) to select
5693+
// -(a-b), otherwise a-b
56935694
ARMCC::CondCodes CC = (Op.getOpcode() == ISD::ABDS) ? ARMCC::MI : ARMCC::LO;
56945695

5695-
// CSEL: if a > b, select a-b, otherwise b-a
5696+
// CMOV: if a > b, select a-b, otherwise negare
56965697
return DAG.getNode(ARMISD::CMOV, DL, MVT::i32, Cmp.getValue(0), Neg,
56975698
DAG.getConstant(CC, DL, MVT::i32), Cmp.getValue(1));
56985699
}
@@ -14168,6 +14169,48 @@ static SDValue PerformSubCSINCCombine(SDNode *N, SelectionDAG &DAG) {
1416814169
CSINC.getOperand(3));
1416914170
}
1417014171

14172+
static bool isNegatedInteger(SDValue Op) {
14173+
return Op.getOpcode() == ISD::SUB && isNullConstant(Op.getOperand(0));
14174+
}
14175+
14176+
static SDValue getNegatedInteger(SDValue Op, SelectionDAG &DAG) {
14177+
SDLoc DL(Op);
14178+
EVT VT = Op.getValueType();
14179+
SDValue Zero = DAG.getConstant(0, DL, VT);
14180+
return DAG.getNode(ISD::SUB, DL, VT, Zero, Op);
14181+
}
14182+
14183+
// Try to fold
14184+
//
14185+
// (neg (cmov X, Y)) -> (cmov (neg X), (neg Y))
14186+
//
14187+
// The folding helps cmov to be matched with csneg without generating
14188+
// redundant neg instruction.
14189+
static SDValue performNegCMovCombine(SDNode *N, SelectionDAG &DAG) {
14190+
if (!isNegatedInteger(SDValue(N, 0)))
14191+
return SDValue();
14192+
14193+
SDValue CSel = N->getOperand(1);
14194+
if (CSel.getOpcode() != ARMISD::CMOV || !CSel->hasOneUse())
14195+
return SDValue();
14196+
14197+
SDValue N0 = CSel.getOperand(0);
14198+
SDValue N1 = CSel.getOperand(1);
14199+
14200+
// If both of them is not negations, it's not worth the folding as it
14201+
// introduces two additional negations while reducing one negation.
14202+
if (!isNegatedInteger(N0) && !isNegatedInteger(N1))
14203+
return SDValue();
14204+
14205+
SDValue N0N = getNegatedInteger(N0, DAG);
14206+
SDValue N1N = getNegatedInteger(N1, DAG);
14207+
14208+
SDLoc DL(N);
14209+
EVT VT = CSel.getValueType();
14210+
return DAG.getNode(ARMISD::CMOV, DL, VT, N0N, N1N, CSel.getOperand(2),
14211+
CSel.getOperand(3));
14212+
}
14213+
1417114214
/// PerformSUBCombine - Target-specific dag combine xforms for ISD::SUB.
1417214215
///
1417314216
static SDValue PerformSUBCombine(SDNode *N,
@@ -14184,6 +14227,9 @@ static SDValue PerformSUBCombine(SDNode *N,
1418414227
if (SDValue R = PerformSubCSINCCombine(N, DCI.DAG))
1418514228
return R;
1418614229

14230+
if (SDValue Val = performNegCMovCombine(N, DCI.DAG))
14231+
return Val;
14232+
1418714233
if (!Subtarget->hasMVEIntegerOps() || !N->getValueType(0).isVector())
1418814234
return SDValue();
1418914235

‎llvm/test/CodeGen/ARM/abds-neg.ll‎

Lines changed: 15 additions & 30 deletions
Original file line numberDiff line numberDiff line change
@@ -13,8 +13,7 @@ define i8 @abd_ext_i8(i8 %a, i8 %b) nounwind {
1313
; CHECK-ARM-NEXT: lsl r1, r1, #24
1414
; CHECK-ARM-NEXT: asr r0, r0, #24
1515
; CHECK-ARM-NEXT: subs r0, r0, r1, asr #24
16-
; CHECK-ARM-NEXT: rsbmi r0, r0, #0
17-
; CHECK-ARM-NEXT: rsb r0, r0, #0
16+
; CHECK-ARM-NEXT: rsbpl r0, r0, #0
1817
; CHECK-ARM-NEXT: bx lr
1918
;
2019
; CHECK-THUMB-LABEL: abd_ext_i8:
@@ -42,8 +41,7 @@ define i8 @abd_ext_i8_i16(i8 %a, i16 %b) nounwind {
4241
; CHECK-ARM-NEXT: lsl r1, r1, #16
4342
; CHECK-ARM-NEXT: asr r0, r0, #24
4443
; CHECK-ARM-NEXT: subs r0, r0, r1, asr #16
45-
; CHECK-ARM-NEXT: rsbmi r0, r0, #0
46-
; CHECK-ARM-NEXT: rsb r0, r0, #0
44+
; CHECK-ARM-NEXT: rsbpl r0, r0, #0
4745
; CHECK-ARM-NEXT: bx lr
4846
;
4947
; CHECK-THUMB-LABEL: abd_ext_i8_i16:
@@ -71,8 +69,7 @@ define i8 @abd_ext_i8_undef(i8 %a, i8 %b) nounwind {
7169
; CHECK-ARM-NEXT: lsl r1, r1, #24
7270
; CHECK-ARM-NEXT: asr r0, r0, #24
7371
; CHECK-ARM-NEXT: subs r0, r0, r1, asr #24
74-
; CHECK-ARM-NEXT: rsbmi r0, r0, #0
75-
; CHECK-ARM-NEXT: rsb r0, r0, #0
72+
; CHECK-ARM-NEXT: rsbpl r0, r0, #0
7673
; CHECK-ARM-NEXT: bx lr
7774
;
7875
; CHECK-THUMB-LABEL: abd_ext_i8_undef:
@@ -100,8 +97,7 @@ define i16 @abd_ext_i16(i16 %a, i16 %b) nounwind {
10097
; CHECK-ARM-NEXT: lsl r1, r1, #16
10198
; CHECK-ARM-NEXT: asr r0, r0, #16
10299
; CHECK-ARM-NEXT: subs r0, r0, r1, asr #16
103-
; CHECK-ARM-NEXT: rsbmi r0, r0, #0
104-
; CHECK-ARM-NEXT: rsb r0, r0, #0
100+
; CHECK-ARM-NEXT: rsbpl r0, r0, #0
105101
; CHECK-ARM-NEXT: bx lr
106102
;
107103
; CHECK-THUMB-LABEL: abd_ext_i16:
@@ -127,8 +123,7 @@ define i16 @abd_ext_i16_i32(i16 %a, i32 %b) nounwind {
127123
; CHECK-ARM: @ %bb.0:
128124
; CHECK-ARM-NEXT: lsl r0, r0, #16
129125
; CHECK-ARM-NEXT: rsbs r0, r1, r0, asr #16
130-
; CHECK-ARM-NEXT: rsbmi r0, r0, #0
131-
; CHECK-ARM-NEXT: rsb r0, r0, #0
126+
; CHECK-ARM-NEXT: rsbpl r0, r0, #0
132127
; CHECK-ARM-NEXT: bx lr
133128
;
134129
; CHECK-THUMB-LABEL: abd_ext_i16_i32:
@@ -155,8 +150,7 @@ define i16 @abd_ext_i16_undef(i16 %a, i16 %b) nounwind {
155150
; CHECK-ARM-NEXT: lsl r1, r1, #16
156151
; CHECK-ARM-NEXT: asr r0, r0, #16
157152
; CHECK-ARM-NEXT: subs r0, r0, r1, asr #16
158-
; CHECK-ARM-NEXT: rsbmi r0, r0, #0
159-
; CHECK-ARM-NEXT: rsb r0, r0, #0
153+
; CHECK-ARM-NEXT: rsbpl r0, r0, #0
160154
; CHECK-ARM-NEXT: bx lr
161155
;
162156
; CHECK-THUMB-LABEL: abd_ext_i16_undef:
@@ -181,8 +175,7 @@ define i32 @abd_ext_i32(i32 %a, i32 %b) nounwind {
181175
; CHECK-ARM-LABEL: abd_ext_i32:
182176
; CHECK-ARM: @ %bb.0:
183177
; CHECK-ARM-NEXT: subs r0, r0, r1
184-
; CHECK-ARM-NEXT: rsbmi r0, r0, #0
185-
; CHECK-ARM-NEXT: rsb r0, r0, #0
178+
; CHECK-ARM-NEXT: rsbpl r0, r0, #0
186179
; CHECK-ARM-NEXT: bx lr
187180
;
188181
; CHECK-THUMB-LABEL: abd_ext_i32:
@@ -206,8 +199,7 @@ define i32 @abd_ext_i32_i16(i32 %a, i16 %b) nounwind {
206199
; CHECK-ARM: @ %bb.0:
207200
; CHECK-ARM-NEXT: lsl r1, r1, #16
208201
; CHECK-ARM-NEXT: subs r0, r0, r1, asr #16
209-
; CHECK-ARM-NEXT: rsbmi r0, r0, #0
210-
; CHECK-ARM-NEXT: rsb r0, r0, #0
202+
; CHECK-ARM-NEXT: rsbpl r0, r0, #0
211203
; CHECK-ARM-NEXT: bx lr
212204
;
213205
; CHECK-THUMB-LABEL: abd_ext_i32_i16:
@@ -231,8 +223,7 @@ define i32 @abd_ext_i32_undef(i32 %a, i32 %b) nounwind {
231223
; CHECK-ARM-LABEL: abd_ext_i32_undef:
232224
; CHECK-ARM: @ %bb.0:
233225
; CHECK-ARM-NEXT: subs r0, r0, r1
234-
; CHECK-ARM-NEXT: rsbmi r0, r0, #0
235-
; CHECK-ARM-NEXT: rsb r0, r0, #0
226+
; CHECK-ARM-NEXT: rsbpl r0, r0, #0
236227
; CHECK-ARM-NEXT: bx lr
237228
;
238229
; CHECK-THUMB-LABEL: abd_ext_i32_undef:
@@ -546,8 +537,7 @@ define i8 @abd_minmax_i8(i8 %a, i8 %b) nounwind {
546537
; CHECK-ARM-NEXT: lsl r1, r1, #24
547538
; CHECK-ARM-NEXT: asr r0, r0, #24
548539
; CHECK-ARM-NEXT: subs r0, r0, r1, asr #24
549-
; CHECK-ARM-NEXT: rsbmi r0, r0, #0
550-
; CHECK-ARM-NEXT: rsb r0, r0, #0
540+
; CHECK-ARM-NEXT: rsbpl r0, r0, #0
551541
; CHECK-ARM-NEXT: bx lr
552542
;
553543
; CHECK-THUMB-LABEL: abd_minmax_i8:
@@ -572,8 +562,7 @@ define i16 @abd_minmax_i16(i16 %a, i16 %b) nounwind {
572562
; CHECK-ARM-NEXT: lsl r1, r1, #16
573563
; CHECK-ARM-NEXT: asr r0, r0, #16
574564
; CHECK-ARM-NEXT: subs r0, r0, r1, asr #16
575-
; CHECK-ARM-NEXT: rsbmi r0, r0, #0
576-
; CHECK-ARM-NEXT: rsb r0, r0, #0
565+
; CHECK-ARM-NEXT: rsbpl r0, r0, #0
577566
; CHECK-ARM-NEXT: bx lr
578567
;
579568
; CHECK-THUMB-LABEL: abd_minmax_i16:
@@ -595,8 +584,7 @@ define i32 @abd_minmax_i32(i32 %a, i32 %b) nounwind {
595584
; CHECK-ARM-LABEL: abd_minmax_i32:
596585
; CHECK-ARM: @ %bb.0:
597586
; CHECK-ARM-NEXT: subs r0, r0, r1
598-
; CHECK-ARM-NEXT: rsbmi r0, r0, #0
599-
; CHECK-ARM-NEXT: rsb r0, r0, #0
587+
; CHECK-ARM-NEXT: rsbpl r0, r0, #0
600588
; CHECK-ARM-NEXT: bx lr
601589
;
602590
; CHECK-THUMB-LABEL: abd_minmax_i32:
@@ -864,8 +852,7 @@ define i32 @abd_cmp_i32(i32 %a, i32 %b) nounwind {
864852
; CHECK-ARM-LABEL: abd_cmp_i32:
865853
; CHECK-ARM: @ %bb.0:
866854
; CHECK-ARM-NEXT: subs r0, r0, r1
867-
; CHECK-ARM-NEXT: rsbmi r0, r0, #0
868-
; CHECK-ARM-NEXT: rsb r0, r0, #0
855+
; CHECK-ARM-NEXT: rsbpl r0, r0, #0
869856
; CHECK-ARM-NEXT: bx lr
870857
;
871858
; CHECK-THUMB-LABEL: abd_cmp_i32:
@@ -1108,8 +1095,7 @@ define i32 @abd_subnsw_i32(i32 %a, i32 %b) nounwind {
11081095
; CHECK-ARM-LABEL: abd_subnsw_i32:
11091096
; CHECK-ARM: @ %bb.0:
11101097
; CHECK-ARM-NEXT: subs r0, r0, r1
1111-
; CHECK-ARM-NEXT: rsbmi r0, r0, #0
1112-
; CHECK-ARM-NEXT: rsb r0, r0, #0
1098+
; CHECK-ARM-NEXT: rsbpl r0, r0, #0
11131099
; CHECK-ARM-NEXT: bx lr
11141100
;
11151101
; CHECK-THUMB-LABEL: abd_subnsw_i32:
@@ -1129,8 +1115,7 @@ define i32 @abd_subnsw_i32_undef(i32 %a, i32 %b) nounwind {
11291115
; CHECK-ARM-LABEL: abd_subnsw_i32_undef:
11301116
; CHECK-ARM: @ %bb.0:
11311117
; CHECK-ARM-NEXT: subs r0, r0, r1
1132-
; CHECK-ARM-NEXT: rsbmi r0, r0, #0
1133-
; CHECK-ARM-NEXT: rsb r0, r0, #0
1118+
; CHECK-ARM-NEXT: rsbpl r0, r0, #0
11341119
; CHECK-ARM-NEXT: bx lr
11351120
;
11361121
; CHECK-THUMB-LABEL: abd_subnsw_i32_undef:

‎llvm/test/CodeGen/ARM/abdu-neg.ll‎

Lines changed: 13 additions & 26 deletions
Original file line numberDiff line numberDiff line change
@@ -12,8 +12,7 @@ define i8 @abd_ext_i8(i8 %a, i8 %b) nounwind {
1212
; CHECK-ARM-NEXT: and r1, r1, #255
1313
; CHECK-ARM-NEXT: and r0, r0, #255
1414
; CHECK-ARM-NEXT: subs r0, r0, r1
15-
; CHECK-ARM-NEXT: rsblo r0, r0, #0
16-
; CHECK-ARM-NEXT: rsb r0, r0, #0
15+
; CHECK-ARM-NEXT: rsbhs r0, r0, #0
1716
; CHECK-ARM-NEXT: bx lr
1817
;
1918
; CHECK-THUMB-LABEL: abd_ext_i8:
@@ -42,8 +41,7 @@ define i8 @abd_ext_i8_i16(i8 %a, i16 %b) nounwind {
4241
; CHECK-ARM-NEXT: orr r2, r2, #65280
4342
; CHECK-ARM-NEXT: and r1, r1, r2
4443
; CHECK-ARM-NEXT: subs r0, r0, r1
45-
; CHECK-ARM-NEXT: rsblo r0, r0, #0
46-
; CHECK-ARM-NEXT: rsb r0, r0, #0
44+
; CHECK-ARM-NEXT: rsbhs r0, r0, #0
4745
; CHECK-ARM-NEXT: bx lr
4846
;
4947
; CHECK-THUMB-LABEL: abd_ext_i8_i16:
@@ -70,8 +68,7 @@ define i8 @abd_ext_i8_undef(i8 %a, i8 %b) nounwind {
7068
; CHECK-ARM-NEXT: and r1, r1, #255
7169
; CHECK-ARM-NEXT: and r0, r0, #255
7270
; CHECK-ARM-NEXT: subs r0, r0, r1
73-
; CHECK-ARM-NEXT: rsblo r0, r0, #0
74-
; CHECK-ARM-NEXT: rsb r0, r0, #0
71+
; CHECK-ARM-NEXT: rsbhs r0, r0, #0
7572
; CHECK-ARM-NEXT: bx lr
7673
;
7774
; CHECK-THUMB-LABEL: abd_ext_i8_undef:
@@ -100,8 +97,7 @@ define i16 @abd_ext_i16(i16 %a, i16 %b) nounwind {
10097
; CHECK-ARM-NEXT: and r1, r1, r2
10198
; CHECK-ARM-NEXT: and r0, r0, r2
10299
; CHECK-ARM-NEXT: subs r0, r0, r1
103-
; CHECK-ARM-NEXT: rsblo r0, r0, #0
104-
; CHECK-ARM-NEXT: rsb r0, r0, #0
100+
; CHECK-ARM-NEXT: rsbhs r0, r0, #0
105101
; CHECK-ARM-NEXT: bx lr
106102
;
107103
; CHECK-THUMB-LABEL: abd_ext_i16:
@@ -129,8 +125,7 @@ define i16 @abd_ext_i16_i32(i16 %a, i32 %b) nounwind {
129125
; CHECK-ARM-NEXT: orr r2, r2, #65280
130126
; CHECK-ARM-NEXT: and r0, r0, r2
131127
; CHECK-ARM-NEXT: subs r0, r0, r1
132-
; CHECK-ARM-NEXT: rsblo r0, r0, #0
133-
; CHECK-ARM-NEXT: rsb r0, r0, #0
128+
; CHECK-ARM-NEXT: rsbhs r0, r0, #0
134129
; CHECK-ARM-NEXT: bx lr
135130
;
136131
; CHECK-THUMB-LABEL: abd_ext_i16_i32:
@@ -158,8 +153,7 @@ define i16 @abd_ext_i16_undef(i16 %a, i16 %b) nounwind {
158153
; CHECK-ARM-NEXT: and r1, r1, r2
159154
; CHECK-ARM-NEXT: and r0, r0, r2
160155
; CHECK-ARM-NEXT: subs r0, r0, r1
161-
; CHECK-ARM-NEXT: rsblo r0, r0, #0
162-
; CHECK-ARM-NEXT: rsb r0, r0, #0
156+
; CHECK-ARM-NEXT: rsbhs r0, r0, #0
163157
; CHECK-ARM-NEXT: bx lr
164158
;
165159
; CHECK-THUMB-LABEL: abd_ext_i16_undef:
@@ -184,8 +178,7 @@ define i32 @abd_ext_i32(i32 %a, i32 %b) nounwind {
184178
; CHECK-ARM-LABEL: abd_ext_i32:
185179
; CHECK-ARM: @ %bb.0:
186180
; CHECK-ARM-NEXT: subs r0, r0, r1
187-
; CHECK-ARM-NEXT: rsblo r0, r0, #0
188-
; CHECK-ARM-NEXT: rsb r0, r0, #0
181+
; CHECK-ARM-NEXT: rsbhs r0, r0, #0
189182
; CHECK-ARM-NEXT: bx lr
190183
;
191184
; CHECK-THUMB-LABEL: abd_ext_i32:
@@ -211,8 +204,7 @@ define i32 @abd_ext_i32_i16(i32 %a, i16 %b) nounwind {
211204
; CHECK-ARM-NEXT: orr r2, r2, #65280
212205
; CHECK-ARM-NEXT: and r1, r1, r2
213206
; CHECK-ARM-NEXT: subs r0, r0, r1
214-
; CHECK-ARM-NEXT: rsblo r0, r0, #0
215-
; CHECK-ARM-NEXT: rsb r0, r0, #0
207+
; CHECK-ARM-NEXT: rsbhs r0, r0, #0
216208
; CHECK-ARM-NEXT: bx lr
217209
;
218210
; CHECK-THUMB-LABEL: abd_ext_i32_i16:
@@ -236,8 +228,7 @@ define i32 @abd_ext_i32_undef(i32 %a, i32 %b) nounwind {
236228
; CHECK-ARM-LABEL: abd_ext_i32_undef:
237229
; CHECK-ARM: @ %bb.0:
238230
; CHECK-ARM-NEXT: subs r0, r0, r1
239-
; CHECK-ARM-NEXT: rsblo r0, r0, #0
240-
; CHECK-ARM-NEXT: rsb r0, r0, #0
231+
; CHECK-ARM-NEXT: rsbhs r0, r0, #0
241232
; CHECK-ARM-NEXT: bx lr
242233
;
243234
; CHECK-THUMB-LABEL: abd_ext_i32_undef:
@@ -524,8 +515,7 @@ define i8 @abd_minmax_i8(i8 %a, i8 %b) nounwind {
524515
; CHECK-ARM-NEXT: and r1, r1, #255
525516
; CHECK-ARM-NEXT: and r0, r0, #255
526517
; CHECK-ARM-NEXT: subs r0, r0, r1
527-
; CHECK-ARM-NEXT: rsblo r0, r0, #0
528-
; CHECK-ARM-NEXT: rsb r0, r0, #0
518+
; CHECK-ARM-NEXT: rsbhs r0, r0, #0
529519
; CHECK-ARM-NEXT: bx lr
530520
;
531521
; CHECK-THUMB-LABEL: abd_minmax_i8:
@@ -551,8 +541,7 @@ define i16 @abd_minmax_i16(i16 %a, i16 %b) nounwind {
551541
; CHECK-ARM-NEXT: and r1, r1, r2
552542
; CHECK-ARM-NEXT: and r0, r0, r2
553543
; CHECK-ARM-NEXT: subs r0, r0, r1
554-
; CHECK-ARM-NEXT: rsblo r0, r0, #0
555-
; CHECK-ARM-NEXT: rsb r0, r0, #0
544+
; CHECK-ARM-NEXT: rsbhs r0, r0, #0
556545
; CHECK-ARM-NEXT: bx lr
557546
;
558547
; CHECK-THUMB-LABEL: abd_minmax_i16:
@@ -574,8 +563,7 @@ define i32 @abd_minmax_i32(i32 %a, i32 %b) nounwind {
574563
; CHECK-ARM-LABEL: abd_minmax_i32:
575564
; CHECK-ARM: @ %bb.0:
576565
; CHECK-ARM-NEXT: subs r0, r0, r1
577-
; CHECK-ARM-NEXT: rsblo r0, r0, #0
578-
; CHECK-ARM-NEXT: rsb r0, r0, #0
566+
; CHECK-ARM-NEXT: rsbhs r0, r0, #0
579567
; CHECK-ARM-NEXT: bx lr
580568
;
581569
; CHECK-THUMB-LABEL: abd_minmax_i32:
@@ -846,8 +834,7 @@ define i32 @abd_cmp_i32(i32 %a, i32 %b) nounwind {
846834
; CHECK-ARM-LABEL: abd_cmp_i32:
847835
; CHECK-ARM: @ %bb.0:
848836
; CHECK-ARM-NEXT: subs r0, r0, r1
849-
; CHECK-ARM-NEXT: rsblo r0, r0, #0
850-
; CHECK-ARM-NEXT: rsb r0, r0, #0
837+
; CHECK-ARM-NEXT: rsbhs r0, r0, #0
851838
; CHECK-ARM-NEXT: bx lr
852839
;
853840
; CHECK-THUMB-LABEL: abd_cmp_i32:

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