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daniilavdeevdaniilavdeev
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refactoring
1 parent 45b1fe2 commit 9ef39d3

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2 files changed

+98
-133
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2 files changed

+98
-133
lines changed

‎llvm/lib/Target/RISCV/RISCVFrameLowering.cpp‎

Lines changed: 95 additions & 131 deletions
Original file line numberDiff line numberDiff line change
@@ -27,6 +27,88 @@
2727

2828
using namespace llvm;
2929

30+
static unsigned getCaleeSavedRVVNumRegs(const Register &BaseReg) {
31+
return RISCV::VRRegClass.contains(BaseReg) ? 1
32+
: RISCV::VRM2RegClass.contains(BaseReg) ? 2
33+
: RISCV::VRM4RegClass.contains(BaseReg) ? 4
34+
: 8;
35+
}
36+
37+
static MCRegister getRVVBaseRegister(const RISCVRegisterInfo &TRI, const Register &Reg) {
38+
MCRegister BaseReg = TRI.getSubReg(Reg, RISCV::sub_vrm1_0);
39+
// If it's not a grouped vector register, it doesn't have subregister, so
40+
// the base register is just itself.
41+
if (BaseReg == RISCV::NoRegister)
42+
BaseReg = Reg;
43+
return BaseReg;
44+
}
45+
46+
namespace {
47+
48+
struct CFIRestoreRegisterEmitter {
49+
CFIRestoreRegisterEmitter(MachineFunction &, const RISCVSubtarget &) {};
50+
51+
void emit(MachineFunction &MF, MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, const RISCVRegisterInfo &RI, const RISCVInstrInfo &TII, const DebugLoc &DL, const CalleeSavedInfo &CS) const {
52+
Register Reg = CS.getReg();
53+
unsigned CFIIndex = MF.addFrameInst(MCCFIInstruction::createRestore(
54+
nullptr, RI.getDwarfRegNum(Reg, true)));
55+
BuildMI(MBB, MBBI, DL, TII.get(TargetOpcode::CFI_INSTRUCTION))
56+
.addCFIIndex(CFIIndex)
57+
.setMIFlag(MachineInstr::FrameDestroy);
58+
}
59+
};
60+
61+
class CFIStoreRegisterEmitter {
62+
MachineFrameInfo &MFI;
63+
64+
public:
65+
CFIStoreRegisterEmitter(MachineFunction &MF, const RISCVSubtarget &) : MFI{MF.getFrameInfo()} {};
66+
67+
void emit(MachineFunction &MF, MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, const RISCVRegisterInfo &RI, const RISCVInstrInfo &TII, const DebugLoc &DL, const CalleeSavedInfo &CS) const {
68+
int FrameIdx = CS.getFrameIdx();
69+
int64_t Offset = MFI.getObjectOffset(FrameIdx);
70+
Register Reg = CS.getReg();
71+
unsigned CFIIndex = MF.addFrameInst(MCCFIInstruction::createOffset(
72+
nullptr, RI.getDwarfRegNum(Reg, true), Offset));
73+
BuildMI(MBB, MBBI, DL, TII.get(TargetOpcode::CFI_INSTRUCTION))
74+
.addCFIIndex(CFIIndex)
75+
.setMIFlag(MachineInstr::FrameSetup);
76+
}
77+
};
78+
79+
class CFIRestoreRVVRegisterEmitter {
80+
const llvm::RISCVRegisterInfo *TRI;
81+
82+
public:
83+
CFIRestoreRVVRegisterEmitter(MachineFunction &, const RISCVSubtarget &STI) : TRI{STI.getRegisterInfo()} {};
84+
85+
void emit(MachineFunction &MF, MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, const RISCVRegisterInfo &RI, const RISCVInstrInfo &TII, const DebugLoc &DL, const CalleeSavedInfo &CS) const {
86+
MCRegister BaseReg = getRVVBaseRegister(*TRI, CS.getReg());
87+
unsigned NumRegs = getCaleeSavedRVVNumRegs(CS.getReg());
88+
for (unsigned i = 0; i < NumRegs; ++i) {
89+
unsigned CFIIndex = MF.addFrameInst(MCCFIInstruction::createRestore(
90+
nullptr, RI.getDwarfRegNum(BaseReg + i, true)));
91+
BuildMI(MBB, MBBI, DL, TII.get(TargetOpcode::CFI_INSTRUCTION))
92+
.addCFIIndex(CFIIndex)
93+
.setMIFlag(MachineInstr::FrameDestroy);
94+
}
95+
}
96+
};
97+
98+
}
99+
100+
template <typename Emitter>
101+
void RISCVFrameLowering::emitCFIForCSI(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, const SmallVector<CalleeSavedInfo, 8> &CSI) const {
102+
MachineFunction *MF = MBB.getParent();
103+
const RISCVRegisterInfo *RI = STI.getRegisterInfo();
104+
const RISCVInstrInfo *TII = STI.getInstrInfo();
105+
DebugLoc DL = MBB.findDebugLoc(MBBI);
106+
107+
Emitter E{*MF, STI};
108+
for (const auto &CS : CSI)
109+
E.emit(*MF, MBB, MBBI, *RI, *TII, DL, CS);
110+
}
111+
30112
static Align getABIStackAlignment(RISCVABI::ABI ABI) {
31113
if (ABI == RISCVABI::ABI_ILP32E)
32114
return Align(4);
@@ -606,18 +688,7 @@ void RISCVFrameLowering::emitPrologue(MachineFunction &MF,
606688
.addCFIIndex(CFIIndex)
607689
.setMIFlag(MachineInstr::FrameSetup);
608690

609-
const auto &CSI = MFI.getCalleeSavedInfo();
610-
auto PushCSI = getPushOrLibCallsSavedInfo(MF, CSI);
611-
for (const auto &Entry : PushCSI) {
612-
int FrameIdx = Entry.getFrameIdx();
613-
int64_t Offset = MFI.getObjectOffset(FrameIdx);
614-
Register Reg = Entry.getReg();
615-
unsigned CFIIndex = MF.addFrameInst(MCCFIInstruction::createOffset(
616-
nullptr, RI->getDwarfRegNum(Reg, true), Offset));
617-
BuildMI(MBB, MBBI, DL, TII->get(TargetOpcode::CFI_INSTRUCTION))
618-
.addCFIIndex(CFIIndex)
619-
.setMIFlag(MachineInstr::FrameSetup);
620-
}
691+
emitCFIForCSI<CFIStoreRegisterEmitter>(MBB, MBBI, getPushOrLibCallsSavedInfo(MF, MFI.getCalleeSavedInfo()));
621692
}
622693

623694
// FIXME (note copied from Lanai): This appears to be overallocating. Needs
@@ -658,19 +729,8 @@ void RISCVFrameLowering::emitPrologue(MachineFunction &MF,
658729
BuildMI(MBB, MBBI, DL, TII->get(TargetOpcode::CFI_INSTRUCTION))
659730
.addCFIIndex(CFIIndex)
660731
.setMIFlag(MachineInstr::FrameSetup);
661-
662-
const auto &CSI = MFI.getCalleeSavedInfo();
663-
auto PushCSI = getPushOrLibCallsSavedInfo(MF, CSI);
664-
for (const auto &Entry : PushCSI) {
665-
int FrameIdx = Entry.getFrameIdx();
666-
int64_t Offset = MFI.getObjectOffset(FrameIdx);
667-
Register Reg = Entry.getReg();
668-
unsigned CFIIndex = MF.addFrameInst(MCCFIInstruction::createOffset(
669-
nullptr, RI->getDwarfRegNum(Reg, true), Offset));
670-
BuildMI(MBB, MBBI, DL, TII->get(TargetOpcode::CFI_INSTRUCTION))
671-
.addCFIIndex(CFIIndex)
672-
.setMIFlag(MachineInstr::FrameSetup);
673-
}
732+
733+
emitCFIForCSI<CFIStoreRegisterEmitter>(MBB, MBBI, getPushOrLibCallsSavedInfo(MF, MFI.getCalleeSavedInfo()));
674734
}
675735

676736
if (StackSize != 0) {
@@ -699,20 +759,7 @@ void RISCVFrameLowering::emitPrologue(MachineFunction &MF,
699759

700760
// Iterate over list of callee-saved registers and emit .cfi_offset
701761
// directives.
702-
for (const auto &Entry : getUnmanagedCSI(MF, CSI)) {
703-
int FrameIdx = Entry.getFrameIdx();
704-
/*if (FrameIdx >= 0 &&
705-
MFI.getStackID(FrameIdx) == TargetStackID::ScalableVector)
706-
continue;*/
707-
708-
int64_t Offset = MFI.getObjectOffset(FrameIdx);
709-
Register Reg = Entry.getReg();
710-
unsigned CFIIndex = MF.addFrameInst(MCCFIInstruction::createOffset(
711-
nullptr, RI->getDwarfRegNum(Reg, true), Offset));
712-
BuildMI(MBB, MBBI, DL, TII->get(TargetOpcode::CFI_INSTRUCTION))
713-
.addCFIIndex(CFIIndex)
714-
.setMIFlag(MachineInstr::FrameSetup);
715-
}
762+
emitCFIForCSI<CFIStoreRegisterEmitter>(MBB, MBBI, getUnmanagedCSI(MF, CSI));
716763

717764
// Generate new FP.
718765
if (hasFP(MF)) {
@@ -900,7 +947,7 @@ void RISCVFrameLowering::emitEpilogue(MachineFunction &MF,
900947
.setMIFlag(MachineInstr::FrameDestroy);
901948
}
902949

903-
emitCalleeSavedRVVEpilogCFI(MBB, LastFrameDestroy);
950+
emitCFIForCSI<CFIRestoreRVVRegisterEmitter>(MBB, LastFrameDestroy, getRVVCalleeSavedInfo(MF, MFI.getCalleeSavedInfo()));
904951
}
905952

906953
if (FirstSPAdjustAmount) {
@@ -965,14 +1012,7 @@ void RISCVFrameLowering::emitEpilogue(MachineFunction &MF,
9651012
}
9661013

9671014
// Recover callee-saved registers.
968-
for (const auto &Entry : UnmanagedCSI) {
969-
Register Reg = Entry.getReg();
970-
unsigned CFIIndex = MF.addFrameInst(MCCFIInstruction::createRestore(
971-
nullptr, RI->getDwarfRegNum(Reg, true)));
972-
BuildMI(MBB, MBBI, DL, TII->get(TargetOpcode::CFI_INSTRUCTION))
973-
.addCFIIndex(CFIIndex)
974-
.setMIFlag(MachineInstr::FrameDestroy);
975-
}
1015+
emitCFIForCSI<CFIRestoreRegisterEmitter>(MBB, MBBI, UnmanagedCSI);
9761016

9771017
bool ApplyPop = RVFI->isPushable(MF) && MBBI != MBB.end() &&
9781018
MBBI->getOpcode() == RISCV::CM_POP;
@@ -981,7 +1021,7 @@ void RISCVFrameLowering::emitEpilogue(MachineFunction &MF,
9811021
// space. Align the stack size down to a multiple of 16. This is needed for
9821022
// RVE.
9831023
// FIXME: Can we increase the stack size to a multiple of 16 instead?
984-
uint64_t Spimm = std::min(alignDown(StackSize, 16), (uint64_t)48);
1024+
uint64_t Spimm = std::min(alignDown(StackSize, 16), static_cast<uint64_t>(48));
9851025
MBBI->getOperand(1).setImm(Spimm);
9861026
StackSize -= Spimm;
9871027

@@ -993,16 +1033,8 @@ void RISCVFrameLowering::emitEpilogue(MachineFunction &MF,
9931033
if (NextI != MBB.end() && NextI->getOpcode() != RISCV::PseudoRET) {
9941034
++MBBI;
9951035

996-
unsigned PushedRegNum = RVFI->getRVPushRegs();
997-
for (unsigned i = 0; i < PushedRegNum; i++) {
998-
Register Reg = FixedCSRFIMap[i].first;
999-
unsigned CFIIndex = MF.addFrameInst(MCCFIInstruction::createRestore(
1000-
nullptr, RI->getDwarfRegNum(Reg, true)));
1001-
BuildMI(MBB, MBBI, DL, TII->get(TargetOpcode::CFI_INSTRUCTION))
1002-
.addCFIIndex(CFIIndex)
1003-
.setMIFlag(MachineInstr::FrameDestroy);
1004-
}
1005-
1036+
emitCFIForCSI<CFIRestoreRegisterEmitter>(MBB, MBBI, getPushOrLibCallsSavedInfo(MF, MFI.getCalleeSavedInfo()));
1037+
10061038
// Update CFA offset. After CM_POP SP should be equal to CFA, so CFA offset
10071039
// should be a zero.
10081040
unsigned CFIIndex =
@@ -1012,17 +1044,7 @@ void RISCVFrameLowering::emitEpilogue(MachineFunction &MF,
10121044
.setMIFlag(MachineInstr::FrameDestroy);
10131045
}
10141046
}
1015-
/*
1016-
// Recover callee-saved registers.
1017-
for (const auto &Entry : UnmanagedCSI) {
1018-
Register Reg = Entry.getReg();
1019-
unsigned CFIIndex = MF.addFrameInst(MCCFIInstruction::createRestore(
1020-
nullptr, RI->getDwarfRegNum(Reg, true)));
1021-
BuildMI(MBB, MBBI, DL, TII->get(TargetOpcode::CFI_INSTRUCTION))
1022-
.addCFIIndex(CFIIndex)
1023-
.setMIFlag(MachineInstr::FrameDestroy);
1024-
}
1025-
*/
1047+
10261048
// Deallocate stack if StackSize isn't a zero yet
10271049
if (StackSize != 0)
10281050
deallocateStack(MF, MBB, MBBI, DL, StackSize, 0);
@@ -1712,39 +1734,6 @@ bool RISCVFrameLowering::spillCalleeSavedRegisters(
17121734
return true;
17131735
}
17141736

1715-
/*void RISCVFrameLowering::emitPopCFI(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, bool HasFP) const {
1716-
MachineFunction *MF = MBB.getParent();
1717-
RISCVMachineFunctionInfo *RVFI = MF->getInfo<RISCVMachineFunctionInfo>();
1718-
1719-
unsigned PushedRegNum = RVFI->getRVPushRegs();
1720-
for (unsigned idx = 0; idx < PushedRegNum; ++idx) {
1721-
Register Reg = MCOperand::createReg(FixedCSRFIMap[idx].first) ;
1722-
unsigned CFIIndex = MF.addFrameInst(MCCFIInstruction::createRestore(
1723-
nullptr, RI->getDwarfRegNum(Reg, true)));
1724-
BuildMI(MBB, MBBI, DL, TII->get(TargetOpcode::CFI_INSTRUCTION))
1725-
.addCFIIndex(CFIIndex)
1726-
.setMIFlag(MachineInstr::FrameDestroy);
1727-
}
1728-
*/
1729-
1730-
1731-
static unsigned getCaleeSavedRVVNumRegs(const Register &BaseReg) {
1732-
return RISCV::VRRegClass.contains(BaseReg) ? 1
1733-
: RISCV::VRM2RegClass.contains(BaseReg) ? 2
1734-
: RISCV::VRM4RegClass.contains(BaseReg) ? 4
1735-
: 8;
1736-
}
1737-
1738-
static MCRegister getRVVBaseRegister(const RISCVRegisterInfo &TRI, const Register &Reg) {
1739-
MCRegister BaseReg = TRI.getSubReg(Reg, RISCV::sub_vrm1_0);
1740-
// If it's not a grouped vector register, it doesn't have subregister, so
1741-
// the base register is just itself.
1742-
if (BaseReg == RISCV::NoRegister)
1743-
BaseReg = Reg;
1744-
return BaseReg;
1745-
}
1746-
1747-
17481737
void RISCVFrameLowering::emitCalleeSavedRVVPrologCFI(
17491738
MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, bool HasFP) const {
17501739
MachineFunction *MF = MBB.getParent();
@@ -1770,39 +1759,14 @@ void RISCVFrameLowering::emitCalleeSavedRVVPrologCFI(
17701759
for (auto &CS : RVVCSI) {
17711760
// Insert the spill to the stack frame.
17721761
int FI = CS.getFrameIdx();
1773-
if (FI >= 0 && MFI.getStackID(FI) == TargetStackID::ScalableVector) {
1774-
MCRegister BaseReg = getRVVBaseRegister(TRI, CS.getReg());
1775-
unsigned NumRegs = getCaleeSavedRVVNumRegs(CS.getReg());
1776-
for (unsigned i = 0; i < NumRegs; ++i) {
1777-
unsigned CFIIndex = MF->addFrameInst(createDefCFAOffset(
1778-
TRI, BaseReg + i, -FixedSize, MFI.getObjectOffset(FI) / 8 + i));
1779-
BuildMI(MBB, MI, DL, TII.get(TargetOpcode::CFI_INSTRUCTION))
1780-
.addCFIIndex(CFIIndex)
1781-
.setMIFlag(MachineInstr::FrameSetup);
1782-
}
1783-
}
1784-
}
1785-
}
1786-
1787-
void RISCVFrameLowering::emitCalleeSavedRVVEpilogCFI(
1788-
MachineBasicBlock &MBB, MachineBasicBlock::iterator MI) const {
1789-
MachineFunction *MF = MBB.getParent();
1790-
const MachineFrameInfo &MFI = MF->getFrameInfo();
1791-
const RISCVRegisterInfo *RI = STI.getRegisterInfo();
1792-
const TargetInstrInfo &TII = *STI.getInstrInfo();
1793-
const RISCVRegisterInfo &TRI = *STI.getRegisterInfo();
1794-
DebugLoc DL = MBB.findDebugLoc(MI);
1795-
1796-
const auto &RVVCSI = getRVVCalleeSavedInfo(*MF, MFI.getCalleeSavedInfo());
1797-
for (auto &CS : RVVCSI) {
17981762
MCRegister BaseReg = getRVVBaseRegister(TRI, CS.getReg());
17991763
unsigned NumRegs = getCaleeSavedRVVNumRegs(CS.getReg());
18001764
for (unsigned i = 0; i < NumRegs; ++i) {
1801-
unsigned CFIIndex = MF->addFrameInst(MCCFIInstruction::createRestore(
1802-
nullptr, RI->getDwarfRegNum(BaseReg + i, true)));
1765+
unsigned CFIIndex = MF->addFrameInst(createDefCFAOffset(
1766+
TRI, BaseReg + i, -FixedSize, MFI.getObjectOffset(FI) / 8 + i));
18031767
BuildMI(MBB, MI, DL, TII.get(TargetOpcode::CFI_INSTRUCTION))
18041768
.addCFIIndex(CFIIndex)
1805-
.setMIFlag(MachineInstr::FrameDestroy);
1769+
.setMIFlag(MachineInstr::FrameSetup);
18061770
}
18071771
}
18081772
}

‎llvm/lib/Target/RISCV/RISCVFrameLowering.h‎

Lines changed: 3 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -91,11 +91,12 @@ class RISCVFrameLowering : public TargetFrameLowering {
9191
void emitCalleeSavedRVVPrologCFI(MachineBasicBlock &MBB,
9292
MachineBasicBlock::iterator MI,
9393
bool HasFP) const;
94-
void emitCalleeSavedRVVEpilogCFI(MachineBasicBlock &MBB,
95-
MachineBasicBlock::iterator MI) const;
9694
void deallocateStack(MachineFunction &MF, MachineBasicBlock &MBB,
9795
MachineBasicBlock::iterator MBBI, const DebugLoc &DL,
9896
uint64_t &StackSize, int64_t CFAOffset) const;
97+
template <typename Emitter>
98+
void emitCFIForCSI(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI,
99+
const SmallVector<CalleeSavedInfo, 8> &CSI) const;
99100

100101
std::pair<int64_t, Align>
101102
assignRVVStackObjectOffsets(MachineFunction &MF) const;

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