Skip to content

Commit 9f06129

Browse files
MalaySanghiMalaySanghi
authored
[X86][MOVRS] Support MOVRS (#116181)
Ref.: https://cdrdv2.intel.com/v1/dl/getContent/671368
1 parent 251958f commit 9f06129

22 files changed

+656
-1
lines changed

‎.icslock‎

Whitespace-only changes.

‎clang/docs/ReleaseNotes.rst‎

Lines changed: 1 addition & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -752,6 +752,7 @@ X86 Support
752752
- Support ISA of ``AMX-MOVRS``.
753753
- Support ISA of ``AMX-AVX512``.
754754
- Support ISA of ``AMX-TF32``.
755+
- Support ISA of ``MOVRS``.
755756

756757
Arm and AArch64 Support
757758
^^^^^^^^^^^^^^^^^^^^^^^

‎clang/include/clang/Basic/BuiltinsX86.def‎

Lines changed: 3 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -660,6 +660,9 @@ TARGET_BUILTIN(__builtin_ia32_vpdpbuud256, "V8iV8iV8iV8i", "ncV:256:", "avxvnnii
660660
TARGET_BUILTIN(__builtin_ia32_vpdpbuuds128, "V4iV4iV4iV4i", "ncV:128:", "avxvnniint8|avx10.2-256")
661661
TARGET_BUILTIN(__builtin_ia32_vpdpbuuds256, "V8iV8iV8iV8i", "ncV:256:", "avxvnniint8|avx10.2-256")
662662

663+
// MOVRS
664+
TARGET_BUILTIN(__builtin_ia32_prefetchrs, "vvC*", "nc", "movrs")
665+
663666
TARGET_BUILTIN(__builtin_ia32_gather3div2df, "V2dV2dvC*V2OiUcIi", "nV:128:", "avx512vl")
664667
TARGET_BUILTIN(__builtin_ia32_gather3div2di, "V2OiV2OivC*V2OiUcIi", "nV:128:", "avx512vl")
665668
TARGET_BUILTIN(__builtin_ia32_gather3div4df, "V4dV4dvC*V4OiUcIi", "nV:256:", "avx512vl")

‎clang/include/clang/Basic/BuiltinsX86_64.def‎

Lines changed: 6 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -228,6 +228,12 @@ TARGET_BUILTIN(__builtin_ia32_aand64, "vv*SOi", "n", "raoint")
228228
TARGET_BUILTIN(__builtin_ia32_aor64, "vv*SOi", "n", "raoint")
229229
TARGET_BUILTIN(__builtin_ia32_axor64, "vv*SOi", "n", "raoint")
230230

231+
// MOVRS
232+
TARGET_BUILTIN(__builtin_ia32_movrsqi, "ScvC*", "n", "movrs")
233+
TARGET_BUILTIN(__builtin_ia32_movrshi, "SsvC*", "n", "movrs")
234+
TARGET_BUILTIN(__builtin_ia32_movrssi, "SivC*", "n", "movrs")
235+
TARGET_BUILTIN(__builtin_ia32_movrsdi, "SLLivC*", "n", "movrs")
236+
231237
// MOVRS and AVX10.2
232238
TARGET_BUILTIN(__builtin_ia32_vmovrsb128, "V16cV16cC*", "nV:128:", "movrs,avx10.2-256")
233239
TARGET_BUILTIN(__builtin_ia32_vmovrsb256, "V32cV32cC*", "nV:256:", "movrs,avx10.2-256")

‎clang/lib/Headers/CMakeLists.txt‎

Lines changed: 1 addition & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -233,6 +233,7 @@ set(x86_files
233233
movdirintrin.h
234234
movrs_avx10_2_512intrin.h
235235
movrs_avx10_2intrin.h
236+
movrsintrin.h
236237
mwaitxintrin.h
237238
nmmintrin.h
238239
pconfigintrin.h

‎clang/lib/Headers/immintrin.h‎

Lines changed: 4 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -605,6 +605,10 @@ _storebe_i64(void * __P, long long __D) {
605605
#include <movdirintrin.h>
606606
#endif
607607

608+
#if !defined(__SCE__) || __has_feature(modules) || defined(__MOVRS__)
609+
#include <movrsintrin.h>
610+
#endif
611+
608612
#if !defined(__SCE__) || __has_feature(modules) || \
609613
(defined(__AVX10_2__) && defined(__MOVRS__))
610614
#include <movrs_avx10_2intrin.h>

‎clang/lib/Headers/movrsintrin.h‎

Lines changed: 59 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,59 @@
1+
/*===---------------- movrsintrin.h - MOVRS intrinsics ----------------------===
2+
*
3+
* Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4+
* See https://llvm.org/LICENSE.txt for license information.
5+
* SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6+
*
7+
*===----------------------------------------------------------------------===*/
8+
9+
#ifndef __IMMINTRIN_H
10+
#error "Never use <movrsintrin.h> directly; include <immintrin.h> instead."
11+
#endif // __IMMINTRIN_H
12+
13+
#ifndef __MOVRSINTRIN_H
14+
#define __MOVRSINTRIN_H
15+
16+
#define __DEFAULT_FN_ATTRS \
17+
__attribute__((__always_inline__, __nodebug__, __target__("movrs")))
18+
19+
#ifdef __x86_64__
20+
static __inline__ char __DEFAULT_FN_ATTRS _movrs_i8(const void *__A) {
21+
return (char)__builtin_ia32_movrsqi((const void *)__A);
22+
}
23+
24+
static __inline__ short __DEFAULT_FN_ATTRS _movrs_i16(const void *__A) {
25+
return (short)__builtin_ia32_movrshi((const void *)__A);
26+
}
27+
28+
static __inline__ int __DEFAULT_FN_ATTRS _movrs_i32(const void *__A) {
29+
return (int)__builtin_ia32_movrssi((const void *)__A);
30+
}
31+
32+
static __inline__ long long __DEFAULT_FN_ATTRS _movrs_i64(const void *__A) {
33+
return (long long)__builtin_ia32_movrsdi((const void *)__A);
34+
}
35+
#endif // __x86_64__
36+
37+
// Loads a memory sequence containing the specified memory address into
38+
/// the L3 data cache. Data will be shared (read/written) to by requesting
39+
/// core and other cores.
40+
///
41+
/// Note that the effect of this intrinsic is dependent on the processor
42+
/// implementation.
43+
///
44+
/// \headerfile <x86intrin.h>
45+
///
46+
/// This intrinsic corresponds to the \c PREFETCHRS instruction.
47+
///
48+
/// \param __P
49+
/// A pointer specifying the memory address to be prefetched.
50+
static __inline__ void __DEFAULT_FN_ATTRS
51+
_m_prefetchrs(volatile const void *__P) {
52+
#pragma clang diagnostic push
53+
#pragma clang diagnostic ignored "-Wcast-qual"
54+
__builtin_ia32_prefetchrs((const void *)__P);
55+
#pragma clang diagnostic pop
56+
}
57+
58+
#undef __DEFAULT_FN_ATTRS
59+
#endif // __MOVRSINTRIN_H

‎clang/test/CodeGen/X86/movrs-builtins.c‎

Lines changed: 35 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,35 @@
1+
// RUN: %clang_cc1 %s -flax-vector-conversions=none -ffreestanding -triple=x86_64-unknown-unknown -target-feature +movrs \
2+
// RUN: -emit-llvm -o - -Wall -Werror -pedantic -Wno-gnu-statement-expression | FileCheck %s
3+
4+
#include <immintrin.h>
5+
#include <stddef.h>
6+
7+
char test_movrs_si8(const char * __A) {
8+
// CHECK-LABEL: @test_movrs_si8(
9+
// CHECK: call i8 @llvm.x86.movrsqi(
10+
return _movrs_i8(__A);
11+
}
12+
13+
short test_movrs_si16(const short * __A) {
14+
// CHECK-LABEL: @test_movrs_si16(
15+
// CHECK: call i16 @llvm.x86.movrshi(
16+
return _movrs_i16(__A);
17+
}
18+
19+
int test_movrs_si32(const int * __A) {
20+
// CHECK-LABEL: @test_movrs_si32(
21+
// CHECK: call i32 @llvm.x86.movrssi(
22+
return _movrs_i32(__A);
23+
}
24+
25+
long long test_movrs_si64(const long long * __A) {
26+
// CHECK-LABEL: @test_movrs_si64(
27+
// CHECK: call i64 @llvm.x86.movrsdi(
28+
return _movrs_i64(__A);
29+
}
30+
31+
void test_m_prefetch_rs(void *p) {
32+
_m_prefetchrs(p);
33+
// CHECK-LABEL: define{{.*}} void @test_m_prefetch_rs
34+
// CHECK: call void @llvm.x86.prefetchrs({{.*}})
35+
}

‎llvm/include/llvm/IR/IntrinsicsX86.td‎

Lines changed: 17 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -7877,3 +7877,20 @@ def int_x86_avx10_vmovrsw512 : ClangBuiltin<"__builtin_ia32_vmovrsw512">,
78777877
DefaultAttrsIntrinsic<[llvm_v32i16_ty], [llvm_ptr_ty],
78787878
[IntrReadMem]>;
78797879
}
7880+
7881+
let TargetPrefix = "x86" in {
7882+
def int_x86_movrsqi : ClangBuiltin<"__builtin_ia32_movrsqi">,
7883+
Intrinsic<[llvm_i8_ty], [llvm_ptr_ty],
7884+
[IntrReadMem]>;
7885+
def int_x86_movrshi : ClangBuiltin<"__builtin_ia32_movrshi">,
7886+
Intrinsic<[llvm_i16_ty], [llvm_ptr_ty],
7887+
[IntrReadMem]>;
7888+
def int_x86_movrssi : ClangBuiltin<"__builtin_ia32_movrssi">,
7889+
Intrinsic<[llvm_i32_ty], [llvm_ptr_ty],
7890+
[IntrReadMem]>;
7891+
def int_x86_movrsdi : ClangBuiltin<"__builtin_ia32_movrsdi">,
7892+
Intrinsic<[llvm_i64_ty], [llvm_ptr_ty],
7893+
[IntrReadMem]>;
7894+
def int_x86_prefetchrs : ClangBuiltin<"__builtin_ia32_prefetchrs">,
7895+
Intrinsic<[], [llvm_ptr_ty], []>;
7896+
}

‎llvm/lib/Target/X86/X86DiscriminateMemOps.cpp‎

Lines changed: 2 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -71,7 +71,8 @@ class X86DiscriminateMemOps : public MachineFunctionPass {
7171
bool IsPrefetchOpcode(unsigned Opcode) {
7272
return Opcode == X86::PREFETCHNTA || Opcode == X86::PREFETCHT0 ||
7373
Opcode == X86::PREFETCHT1 || Opcode == X86::PREFETCHT2 ||
74-
Opcode == X86::PREFETCHIT0 || Opcode == X86::PREFETCHIT1;
74+
Opcode == X86::PREFETCHIT0 || Opcode == X86::PREFETCHIT1 ||
75+
Opcode == X86::PREFETCHRST2;
7576
}
7677
} // end anonymous namespace
7778

0 commit comments

Comments
 (0)