Address review comments

Change-Id: I8b50f54a8eab9e78ef40c8002eb1768cb8e0bdb7

Author: MacDue

llvm/lib/Target/AArch64/AArch64ExpandPseudoInsts.cpp

@@ -1018,11 +1018,9 @@ AArch64ExpandPseudo::expandCommitOrRestoreZA(MachineBasicBlock &MBB,
   // Replace the pseudo with a call (BL).
   MachineInstrBuilder MIB =
       BuildMI(*SMBB, SMBB->end(), DL, TII->get(AArch64::BL));
-  unsigned FirstBLOperand = 1;
-  if (IsRestoreZA) {
+  if (IsRestoreZA)
     MIB.addReg(MI.getOperand(1).getReg(), RegState::Implicit);
-    FirstBLOperand = 2;
-  }
+  unsigned FirstBLOperand = IsRestoreZA ? 2 : 1;
   for (unsigned I = FirstBLOperand; I < MI.getNumOperands(); ++I)
     MIB.add(MI.getOperand(I));
   BuildMI(SMBB, DL, TII->get(AArch64::B)).addMBB(EndBB);

llvm/lib/Target/AArch64/AArch64ISelLowering.cpp

@@ -9009,9 +9009,6 @@ AArch64TargetLowering::LowerCall(CallLoweringInfo &CLI,
   if (MF.getTarget().Options.EmitCallGraphSection && CB && CB->isIndirectCall())
     CSInfo = MachineFunction::CallSiteInfo(*CB);
 
-  // Determine whether we need any streaming mode changes.
-  SMECallAttrs CallAttrs = getSMECallAttrs(MF.getFunction(), CLI);
-
   // Check callee args/returns for SVE registers and set calling convention
   // accordingly.
   if (CallConv == CallingConv::C || CallConv == CallingConv::Fast) {
@@ -9025,6 +9022,8 @@ AArch64TargetLowering::LowerCall(CallLoweringInfo &CLI,
       CallConv = CallingConv::AArch64_SVE_VectorCall;
   }
 
+  // Determine whether we need any streaming mode changes.
+  SMECallAttrs CallAttrs = getSMECallAttrs(MF.getFunction(), CLI);
   bool UseNewSMEABILowering = Subtarget->useNewSMEABILowering();
   bool IsAgnosticZAFunction = CallAttrs.caller().hasAgnosticZAInterface();
   auto ZAMarkerNode = [&]() -> std::optional<unsigned> {
@@ -9043,7 +9042,7 @@ AArch64TargetLowering::LowerCall(CallLoweringInfo &CLI,
 
     // A sibling call is one where we're under the usual C ABI and not planning
     // to change that but can still do a tail call:
-    if (!ZAMarkerNode.has_value() && !TailCallOpt && IsTailCall &&
+    if (!ZAMarkerNode && !TailCallOpt && IsTailCall &&
         CallConv != CallingConv::Tail && CallConv != CallingConv::SwiftTail)
       IsSibCall = true;
 
@@ -9199,8 +9198,8 @@ AArch64TargetLowering::LowerCall(CallLoweringInfo &CLI,
     Chain = DAG.getCALLSEQ_START(Chain, IsTailCall ? 0 : NumBytes, 0, DL);
     if (ZAMarkerNode) {
       // Note: We need the CALLSEQ_START to glue the ZAMarkerNode to, simply
-      // using a chain can result in incorrect scheduling. The markers referer
-      // to the position just before the CALLSEQ_START (though occur after as
+      // using a chain can result in incorrect scheduling. The markers refer to
+      // the position just before the CALLSEQ_START (though occur after as
       // CALLSEQ_START lacks in-glue).
       Chain = DAG.getNode(*ZAMarkerNode, DL, DAG.getVTList(MVT::Other),
                           {Chain, Chain.getValue(1)});

llvm/lib/Target/AArch64/AArch64SMEInstrInfo.td

@@ -92,7 +92,7 @@ let hasSideEffects = 1 in {
 
 def CommitZAPseudo
   : Pseudo<(outs),
-           (ins GPR64:$tpidr2_el0, i64imm:$restore_routine, variable_ops), []>,
+           (ins GPR64:$tpidr2_el0, i64imm:$commit_routine, variable_ops), []>,
            Sched<[]>;
 
 def AArch64_inout_za_use

llvm/lib/Target/AArch64/AArch64TargetMachine.cpp

@@ -824,7 +824,7 @@ bool AArch64PassConfig::addILPOpts() {
 }
 
 void AArch64PassConfig::addPreRegAlloc() {
-  if (EnableNewSMEABILowering && TM->getOptLevel() == CodeGenOptLevel::None)
+  if (TM->getOptLevel() == CodeGenOptLevel::None && EnableNewSMEABILowering)
     addPass(createMachineSMEABIPass());
 
   // Change dead register definitions to refer to the zero register.