Re-use RegInfo HwMode kind

Author: arsenm

llvm/include/llvm/MC/MCSubtargetInfo.h

@@ -255,11 +255,10 @@ class LLVM_ABI MCSubtargetInfo {
   /// this method also supports controlling multiple attributes with a single
   /// HwMode ID, just as was done previously.
   enum HwModeType {
-    HwMode_Default,   // Return the smallest HwMode ID of current subtarget.
-    HwMode_ValueType, // Return the HwMode ID that controls the ValueType.
-    HwMode_RegInfo,   // Return the HwMode ID that controls the RegSizeInfo and
-                      // SubRegRange.
-    HwMode_RegClass,  // Return the HwMode ID that controls the RegisterClass.
+    HwMode_Default,     // Return the smallest HwMode ID of current subtarget.
+    HwMode_ValueType,   // Return the HwMode ID that controls the ValueType.
+    HwMode_RegInfo,     // Return the HwMode ID that controls the RegSizeInfo,
+                        // SubRegRange, and RegisterClass.
     HwMode_EncodingInfo // Return the HwMode ID that controls the EncodingInfo.
   };
 

llvm/test/TableGen/RegClassByHwMode.td

@@ -97,7 +97,7 @@ include "llvm/Target/Target.td"
 // ASMMATCHER-NEXT:    };
 // ASMMATCHER-EMPTY:
 // ASMMATCHER-NEXT:    static_assert(MCK_LAST_REGCLASS_BY_HWMODE - MCK_LAST_REGISTER == 3);
-// ASMMATCHER-NEXT:    const unsigned HwMode = STI.getHwMode(MCSubtargetInfo::HwMode_RegClass);
+// ASMMATCHER-NEXT:    const unsigned HwMode = STI.getHwMode(MCSubtargetInfo::HwMode_RegInfo);
 // ASMMATCHER-NEXT:    Kind = RegClassByHwModeMatchTable[HwMode][Kind - (MCK_LAST_REGISTER + 1)];
 // ASMMATCHER-NEXT:  }
 
@@ -116,7 +116,7 @@ include "llvm/Target/Target.td"
 
 // DISASM{LITERAL}: [[maybe_unused]]
 // DISASM-NEXT: static DecodeStatus DecodeMyPtrRCRegClassByHwMode(MCInst &Inst, unsigned Imm, uint64_t Addr, const MCDisassembler *Decoder) {
-// DISASM-NEXT:   switch (Decoder->getSubtargetInfo().getHwMode(MCSubtargetInfo::HwMode_RegClass)) {
+// DISASM-NEXT:   switch (Decoder->getSubtargetInfo().getHwMode(MCSubtargetInfo::HwMode_RegInfo)) {
 // DISASM-NEXT:   case 0: // DefaultMode
 // DISASM-NEXT:     return DecodePtrRegs32RegisterClass(Inst, Imm, Addr, Decoder);
 // DISASM-NEXT:   case 3: // Ptr64
@@ -128,7 +128,7 @@ include "llvm/Target/Target.td"
 
 // DISASM{LITERAL}: [[maybe_unused]]
 // DISASM-NEXT: static DecodeStatus DecodeXRegs_EvenIfRequiredRegClassByHwMode(MCInst &Inst, unsigned Imm, uint64_t Addr, const MCDisassembler *Decoder) {
-// DISASM-NEXT:  switch (Decoder->getSubtargetInfo().getHwMode(MCSubtargetInfo::HwMode_RegClass)) {
+// DISASM-NEXT:  switch (Decoder->getSubtargetInfo().getHwMode(MCSubtargetInfo::HwMode_RegInfo)) {
 // DISASM-NEXT:  case 0: // DefaultMode
 // DISASM-NEXT:    return DecodeXRegsRegisterClass(Inst, Imm, Addr, Decoder);
 // DISASM-NEXT:  case 1: // EvenMode
@@ -142,7 +142,7 @@ include "llvm/Target/Target.td"
 // DISASM-EMPTY:
 // DISASM{LITERAL}: [[maybe_unused]]
 // DISASM-NEXT: static DecodeStatus DecodeYRegs_EvenIfRequiredRegClassByHwMode(MCInst &Inst, unsigned Imm, uint64_t Addr, const MCDisassembler *Decoder) {
-// DISASM-NEXT:  switch (Decoder->getSubtargetInfo().getHwMode(MCSubtargetInfo::HwMode_RegClass)) {
+// DISASM-NEXT:  switch (Decoder->getSubtargetInfo().getHwMode(MCSubtargetInfo::HwMode_RegInfo)) {
 // DISASM-NEXT:  case 0: // DefaultMode
 // DISASM-NEXT:    return DecodeYRegsRegisterClass(Inst, Imm, Addr, Decoder);
 // DISASM-NEXT:  case 1: // EvenMode

llvm/utils/TableGen/AsmMatcherEmitter.cpp

@@ -2606,7 +2606,7 @@ static void emitValidateOperandClass(const CodeGenTarget &Target,
 
     OS << indent(4)
        << "const unsigned HwMode = "
-          "STI.getHwMode(MCSubtargetInfo::HwMode_RegClass);\n"
+          "STI.getHwMode(MCSubtargetInfo::HwMode_RegInfo);\n"
           "Kind = RegClassByHwModeMatchTable[HwMode][Kind - (MCK_LAST_REGISTER "
           "+ 1)];\n"
           "  }\n\n";

llvm/utils/TableGen/DecoderEmitter.cpp

@@ -864,8 +864,6 @@ void DecoderEmitter::emitRegClassByHwModeDecoders(
   if (RegClassByHwMode.empty())
     return;
 
-  const CodeGenRegBank &RegBank = Target.getRegBank();
-
   for (const Record *ClassByHwMode : RegClassByHwMode) {
     // Ignore cases that had an explicit DecoderMethod set.
     if (!InstructionEncoding::findOperandDecoderMethod(Target, ClassByHwMode)
@@ -882,11 +880,9 @@ void DecoderEmitter::emitRegClassByHwModeDecoders(
     OS << "static DecodeStatus Decode" << ClassByHwMode->getName()
        << "RegClassByHwMode";
     OS << R"((MCInst &Inst, unsigned Imm, uint64_t Addr, const MCDisassembler *Decoder) {
-  switch (Decoder->getSubtargetInfo().getHwMode(MCSubtargetInfo::HwMode_RegClass)) {
+  switch (Decoder->getSubtargetInfo().getHwMode(MCSubtargetInfo::HwMode_RegInfo)) {
 )";
     for (auto [ModeID, RegClassRec] : ModeSelect.Items) {
-      const CodeGenRegisterClass *RegClass = RegBank.getRegClass(RegClassRec);
-
       OS << indent(2) << "case " << ModeID << ": // "
          << CGH.getModeName(ModeID, /*IncludeDefault=*/true) << '\n'
          << indent(4) << "return "

llvm/utils/TableGen/InstrInfoEmitter.cpp

@@ -1181,7 +1181,7 @@ void InstrInfoEmitter::run(raw_ostream &OS) {
   if (NumClassesByHwMode != 0)
     OS << ", " << TargetName
        << "RegClassByHwModeTables[STI.getHwMode(MCSubtargetInfo::HwMode_"
-          "RegClass)]";
+          "RegInfo)]";
 
   OS << ") {\n"
      << "  InitMCInstrInfo(" << TargetName << "Descs.Insts, " << TargetName

llvm/utils/TableGen/SubtargetEmitter.cpp

@@ -1850,7 +1850,6 @@ void SubtargetEmitter::emitHwModeCheck(const std::string &ClassName,
   OS << "  case HwMode_Default:\n    return llvm::countr_zero(Modes) + 1;\n";
   HandlePerMode("ValueType", ValueTypeModes);
   HandlePerMode("RegInfo", RegInfoModes);
-  HandlePerMode("RegClass", RegInfoModes);
   HandlePerMode("EncodingInfo", EncodingInfoModes);
   OS << "  }\n";
   OS << "  llvm_unreachable(\"unexpected HwModeType\");\n"