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[DAGCombiner] Fold vector subtraction if above threshold to umin (#148834)
This extends #134235 and #135194 to vectors.
1 parent ba5f31c commit 9fa3971

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+122
-141
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3 files changed

+122
-141
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‎llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp

Lines changed: 54 additions & 33 deletions
Original file line numberDiff line numberDiff line change
@@ -609,6 +609,8 @@ namespace {
609609
SDValue foldABSToABD(SDNode *N, const SDLoc &DL);
610610
SDValue foldSelectToABD(SDValue LHS, SDValue RHS, SDValue True,
611611
SDValue False, ISD::CondCode CC, const SDLoc &DL);
612+
SDValue foldSelectToUMin(SDValue LHS, SDValue RHS, SDValue True,
613+
SDValue False, ISD::CondCode CC, const SDLoc &DL);
612614
SDValue unfoldMaskedMerge(SDNode *N);
613615
SDValue unfoldExtremeBitClearingToShifts(SDNode *N);
614616
SDValue SimplifySetCC(EVT VT, SDValue N0, SDValue N1, ISD::CondCode Cond,
@@ -859,7 +861,7 @@ namespace {
859861
auto LK = TLI.getTypeConversion(*DAG.getContext(), VT);
860862
return (LK.first == TargetLoweringBase::TypeLegal ||
861863
LK.first == TargetLoweringBase::TypePromoteInteger) &&
862-
TLI.isOperationLegal(ISD::UMIN, LK.second);
864+
TLI.isOperationLegalOrCustom(ISD::UMIN, LK.second);
863865
}
864866

865867
public:
@@ -4093,6 +4095,26 @@ SDValue DAGCombiner::visitSUB(SDNode *N) {
40934095
return N0;
40944096
}
40954097

4098+
// (sub x, ([v]select (ult x, y), 0, y)) -> (umin x, (sub x, y))
4099+
// (sub x, ([v]select (uge x, y), y, 0)) -> (umin x, (sub x, y))
4100+
if (N1.hasOneUse() && hasUMin(VT)) {
4101+
SDValue Y;
4102+
if (sd_match(N1, m_Select(m_SetCC(m_Specific(N0), m_Value(Y),
4103+
m_SpecificCondCode(ISD::SETULT)),
4104+
m_Zero(), m_Deferred(Y))) ||
4105+
sd_match(N1, m_Select(m_SetCC(m_Specific(N0), m_Value(Y),
4106+
m_SpecificCondCode(ISD::SETUGE)),
4107+
m_Deferred(Y), m_Zero())) ||
4108+
sd_match(N1, m_VSelect(m_SetCC(m_Specific(N0), m_Value(Y),
4109+
m_SpecificCondCode(ISD::SETULT)),
4110+
m_Zero(), m_Deferred(Y))) ||
4111+
sd_match(N1, m_VSelect(m_SetCC(m_Specific(N0), m_Value(Y),
4112+
m_SpecificCondCode(ISD::SETUGE)),
4113+
m_Deferred(Y), m_Zero())))
4114+
return DAG.getNode(ISD::UMIN, DL, VT, N0,
4115+
DAG.getNode(ISD::SUB, DL, VT, N0, Y));
4116+
}
4117+
40964118
if (SDValue NewSel = foldBinOpIntoSelect(N))
40974119
return NewSel;
40984120

@@ -4442,20 +4464,6 @@ SDValue DAGCombiner::visitSUB(SDNode *N) {
44424464
sd_match(N1, m_UMaxLike(m_Specific(A), m_Specific(B))))
44434465
return DAG.getNegative(DAG.getNode(ISD::ABDU, DL, VT, A, B), DL, VT);
44444466

4445-
// (sub x, (select (ult x, y), 0, y)) -> (umin x, (sub x, y))
4446-
// (sub x, (select (uge x, y), y, 0)) -> (umin x, (sub x, y))
4447-
if (hasUMin(VT)) {
4448-
SDValue Y;
4449-
if (sd_match(N1, m_OneUse(m_Select(m_SetCC(m_Specific(N0), m_Value(Y),
4450-
m_SpecificCondCode(ISD::SETULT)),
4451-
m_Zero(), m_Deferred(Y)))) ||
4452-
sd_match(N1, m_OneUse(m_Select(m_SetCC(m_Specific(N0), m_Value(Y),
4453-
m_SpecificCondCode(ISD::SETUGE)),
4454-
m_Deferred(Y), m_Zero()))))
4455-
return DAG.getNode(ISD::UMIN, DL, VT, N0,
4456-
DAG.getNode(ISD::SUB, DL, VT, N0, Y));
4457-
}
4458-
44594467
return SDValue();
44604468
}
44614469

@@ -12173,6 +12181,30 @@ SDValue DAGCombiner::foldSelectToABD(SDValue LHS, SDValue RHS, SDValue True,
1217312181
return SDValue();
1217412182
}
1217512183

12184+
// ([v]select (ugt x, C), (add x, ~C), x) -> (umin (add x, ~C), x)
12185+
// ([v]select (ult x, C), x, (add x, -C)) -> (umin x, (add x, -C))
12186+
SDValue DAGCombiner::foldSelectToUMin(SDValue LHS, SDValue RHS, SDValue True,
12187+
SDValue False, ISD::CondCode CC,
12188+
const SDLoc &DL) {
12189+
APInt C;
12190+
EVT VT = True.getValueType();
12191+
if (sd_match(RHS, m_ConstInt(C)) && hasUMin(VT)) {
12192+
if (CC == ISD::SETUGT && LHS == False &&
12193+
sd_match(True, m_Add(m_Specific(False), m_SpecificInt(~C)))) {
12194+
SDValue AddC = DAG.getConstant(~C, DL, VT);
12195+
SDValue Add = DAG.getNode(ISD::ADD, DL, VT, False, AddC);
12196+
return DAG.getNode(ISD::UMIN, DL, VT, Add, False);
12197+
}
12198+
if (CC == ISD::SETULT && LHS == True &&
12199+
sd_match(False, m_Add(m_Specific(True), m_SpecificInt(-C)))) {
12200+
SDValue AddC = DAG.getConstant(-C, DL, VT);
12201+
SDValue Add = DAG.getNode(ISD::ADD, DL, VT, True, AddC);
12202+
return DAG.getNode(ISD::UMIN, DL, VT, True, Add);
12203+
}
12204+
}
12205+
return SDValue();
12206+
}
12207+
1217612208
SDValue DAGCombiner::visitSELECT(SDNode *N) {
1217712209
SDValue N0 = N->getOperand(0);
1217812210
SDValue N1 = N->getOperand(1);
@@ -12358,24 +12390,8 @@ SDValue DAGCombiner::visitSELECT(SDNode *N) {
1235812390

1235912391
// (select (ugt x, C), (add x, ~C), x) -> (umin (add x, ~C), x)
1236012392
// (select (ult x, C), x, (add x, -C)) -> (umin x, (add x, -C))
12361-
APInt C;
12362-
if (sd_match(Cond1, m_ConstInt(C)) && hasUMin(VT)) {
12363-
if (CC == ISD::SETUGT && Cond0 == N2 &&
12364-
sd_match(N1, m_Add(m_Specific(N2), m_SpecificInt(~C)))) {
12365-
// The resulting code relies on an unsigned wrap in ADD.
12366-
// Recreating ADD to drop possible nuw/nsw flags.
12367-
SDValue AddC = DAG.getConstant(~C, DL, VT);
12368-
SDValue Add = DAG.getNode(ISD::ADD, DL, VT, N2, AddC);
12369-
return DAG.getNode(ISD::UMIN, DL, VT, Add, N2);
12370-
}
12371-
if (CC == ISD::SETULT && Cond0 == N1 &&
12372-
sd_match(N2, m_Add(m_Specific(N1), m_SpecificInt(-C)))) {
12373-
// Ditto.
12374-
SDValue AddC = DAG.getConstant(-C, DL, VT);
12375-
SDValue Add = DAG.getNode(ISD::ADD, DL, VT, N1, AddC);
12376-
return DAG.getNode(ISD::UMIN, DL, VT, N1, Add);
12377-
}
12378-
}
12393+
if (SDValue UMin = foldSelectToUMin(Cond0, Cond1, N1, N2, CC, DL))
12394+
return UMin;
1237912395
}
1238012396

1238112397
if (!VT.isVector())
@@ -13412,6 +13428,11 @@ SDValue DAGCombiner::visitVSELECT(SDNode *N) {
1341213428
}
1341313429
}
1341413430
}
13431+
13432+
// (vselect (ugt x, C), (add x, ~C), x) -> (umin (add x, ~C), x)
13433+
// (vselect (ult x, C), x, (add x, -C)) -> (umin x, (add x, -C))
13434+
if (SDValue UMin = foldSelectToUMin(LHS, RHS, N1, N2, CC, DL))
13435+
return UMin;
1341513436
}
1341613437

1341713438
if (SimplifySelectOps(N, N1, N2))

‎llvm/test/CodeGen/RISCV/rvv/fixed-vectors-int.ll

Lines changed: 34 additions & 54 deletions
Original file line numberDiff line numberDiff line change
@@ -5712,9 +5712,8 @@ define <8 x i8> @vsub_if_uge_v8i8(<8 x i8> %va, <8 x i8> %vb) {
57125712
; CHECK-LABEL: vsub_if_uge_v8i8:
57135713
; CHECK: # %bb.0:
57145714
; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, ma
5715-
; CHECK-NEXT: vmsltu.vv v0, v8, v9
57165715
; CHECK-NEXT: vsub.vv v9, v8, v9
5717-
; CHECK-NEXT: vmerge.vvm v8, v9, v8, v0
5716+
; CHECK-NEXT: vminu.vv v8, v8, v9
57185717
; CHECK-NEXT: ret
57195718
%cmp = icmp ult <8 x i8> %va, %vb
57205719
%select = select <8 x i1> %cmp, <8 x i8> zeroinitializer, <8 x i8> %vb
@@ -5725,9 +5724,9 @@ define <8 x i8> @vsub_if_uge_v8i8(<8 x i8> %va, <8 x i8> %vb) {
57255724
define <8 x i8> @vsub_if_uge_swapped_v8i8(<8 x i8> %va, <8 x i8> %vb) {
57265725
; CHECK-LABEL: vsub_if_uge_swapped_v8i8:
57275726
; CHECK: # %bb.0:
5728-
; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, mu
5729-
; CHECK-NEXT: vmsleu.vv v0, v9, v8
5730-
; CHECK-NEXT: vsub.vv v8, v8, v9, v0.t
5727+
; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, ma
5728+
; CHECK-NEXT: vsub.vv v9, v8, v9
5729+
; CHECK-NEXT: vminu.vv v8, v8, v9
57315730
; CHECK-NEXT: ret
57325731
%cmp = icmp uge <8 x i8> %va, %vb
57335732
%select = select <8 x i1> %cmp, <8 x i8> %vb, <8 x i8> zeroinitializer
@@ -5739,9 +5738,8 @@ define <8 x i16> @vsub_if_uge_v8i16(<8 x i16> %va, <8 x i16> %vb) {
57395738
; CHECK-LABEL: vsub_if_uge_v8i16:
57405739
; CHECK: # %bb.0:
57415740
; CHECK-NEXT: vsetivli zero, 8, e16, m1, ta, ma
5742-
; CHECK-NEXT: vmsltu.vv v0, v8, v9
57435741
; CHECK-NEXT: vsub.vv v9, v8, v9
5744-
; CHECK-NEXT: vmerge.vvm v8, v9, v8, v0
5742+
; CHECK-NEXT: vminu.vv v8, v8, v9
57455743
; CHECK-NEXT: ret
57465744
%cmp = icmp ult <8 x i16> %va, %vb
57475745
%select = select <8 x i1> %cmp, <8 x i16> zeroinitializer, <8 x i16> %vb
@@ -5752,9 +5750,9 @@ define <8 x i16> @vsub_if_uge_v8i16(<8 x i16> %va, <8 x i16> %vb) {
57525750
define <8 x i16> @vsub_if_uge_swapped_v8i16(<8 x i16> %va, <8 x i16> %vb) {
57535751
; CHECK-LABEL: vsub_if_uge_swapped_v8i16:
57545752
; CHECK: # %bb.0:
5755-
; CHECK-NEXT: vsetivli zero, 8, e16, m1, ta, mu
5756-
; CHECK-NEXT: vmsleu.vv v0, v9, v8
5757-
; CHECK-NEXT: vsub.vv v8, v8, v9, v0.t
5753+
; CHECK-NEXT: vsetivli zero, 8, e16, m1, ta, ma
5754+
; CHECK-NEXT: vsub.vv v9, v8, v9
5755+
; CHECK-NEXT: vminu.vv v8, v8, v9
57585756
; CHECK-NEXT: ret
57595757
%cmp = icmp uge <8 x i16> %va, %vb
57605758
%select = select <8 x i1> %cmp, <8 x i16> %vb, <8 x i16> zeroinitializer
@@ -5766,9 +5764,8 @@ define <4 x i32> @vsub_if_uge_v4i32(<4 x i32> %va, <4 x i32> %vb) {
57665764
; CHECK-LABEL: vsub_if_uge_v4i32:
57675765
; CHECK: # %bb.0:
57685766
; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, ma
5769-
; CHECK-NEXT: vmsltu.vv v0, v8, v9
57705767
; CHECK-NEXT: vsub.vv v9, v8, v9
5771-
; CHECK-NEXT: vmerge.vvm v8, v9, v8, v0
5768+
; CHECK-NEXT: vminu.vv v8, v8, v9
57725769
; CHECK-NEXT: ret
57735770
%cmp = icmp ult <4 x i32> %va, %vb
57745771
%select = select <4 x i1> %cmp, <4 x i32> zeroinitializer, <4 x i32> %vb
@@ -5779,9 +5776,9 @@ define <4 x i32> @vsub_if_uge_v4i32(<4 x i32> %va, <4 x i32> %vb) {
57795776
define <4 x i32> @vsub_if_uge_swapped_v4i32(<4 x i32> %va, <4 x i32> %vb) {
57805777
; CHECK-LABEL: vsub_if_uge_swapped_v4i32:
57815778
; CHECK: # %bb.0:
5782-
; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, mu
5783-
; CHECK-NEXT: vmsleu.vv v0, v9, v8
5784-
; CHECK-NEXT: vsub.vv v8, v8, v9, v0.t
5779+
; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, ma
5780+
; CHECK-NEXT: vsub.vv v9, v8, v9
5781+
; CHECK-NEXT: vminu.vv v8, v8, v9
57855782
; CHECK-NEXT: ret
57865783
%cmp = icmp uge <4 x i32> %va, %vb
57875784
%select = select <4 x i1> %cmp, <4 x i32> %vb, <4 x i32> zeroinitializer
@@ -5793,9 +5790,8 @@ define <2 x i64> @vsub_if_uge_v2i64(<2 x i64> %va, <2 x i64> %vb) {
57935790
; CHECK-LABEL: vsub_if_uge_v2i64:
57945791
; CHECK: # %bb.0:
57955792
; CHECK-NEXT: vsetivli zero, 2, e64, m1, ta, ma
5796-
; CHECK-NEXT: vmsltu.vv v0, v8, v9
57975793
; CHECK-NEXT: vsub.vv v9, v8, v9
5798-
; CHECK-NEXT: vmerge.vvm v8, v9, v8, v0
5794+
; CHECK-NEXT: vminu.vv v8, v8, v9
57995795
; CHECK-NEXT: ret
58005796
%cmp = icmp ult <2 x i64> %va, %vb
58015797
%select = select <2 x i1> %cmp, <2 x i64> zeroinitializer, <2 x i64> %vb
@@ -5806,9 +5802,9 @@ define <2 x i64> @vsub_if_uge_v2i64(<2 x i64> %va, <2 x i64> %vb) {
58065802
define <2 x i64> @vsub_if_uge_swapped_v2i64(<2 x i64> %va, <2 x i64> %vb) {
58075803
; CHECK-LABEL: vsub_if_uge_swapped_v2i64:
58085804
; CHECK: # %bb.0:
5809-
; CHECK-NEXT: vsetivli zero, 2, e64, m1, ta, mu
5810-
; CHECK-NEXT: vmsleu.vv v0, v9, v8
5811-
; CHECK-NEXT: vsub.vv v8, v8, v9, v0.t
5805+
; CHECK-NEXT: vsetivli zero, 2, e64, m1, ta, ma
5806+
; CHECK-NEXT: vsub.vv v9, v8, v9
5807+
; CHECK-NEXT: vminu.vv v8, v8, v9
58125808
; CHECK-NEXT: ret
58135809
%cmp = icmp uge <2 x i64> %va, %vb
58145810
%select = select <2 x i1> %cmp, <2 x i64> %vb, <2 x i64> zeroinitializer
@@ -5819,9 +5815,9 @@ define <2 x i64> @vsub_if_uge_swapped_v2i64(<2 x i64> %va, <2 x i64> %vb) {
58195815
define <8 x i8> @sub_if_uge_C_v8i8(<8 x i8> %x) {
58205816
; CHECK-LABEL: sub_if_uge_C_v8i8:
58215817
; CHECK: # %bb.0:
5822-
; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, mu
5823-
; CHECK-NEXT: vmsgtu.vi v0, v8, 12
5824-
; CHECK-NEXT: vadd.vi v8, v8, -13, v0.t
5818+
; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, ma
5819+
; CHECK-NEXT: vadd.vi v9, v8, -13
5820+
; CHECK-NEXT: vminu.vv v8, v9, v8
58255821
; CHECK-NEXT: ret
58265822
%cmp = icmp ugt <8 x i8> %x, splat (i8 12)
58275823
%sub = add <8 x i8> %x, splat (i8 -13)
@@ -5832,11 +5828,10 @@ define <8 x i8> @sub_if_uge_C_v8i8(<8 x i8> %x) {
58325828
define <8 x i16> @sub_if_uge_C_v8i16(<8 x i16> %x) {
58335829
; CHECK-LABEL: sub_if_uge_C_v8i16:
58345830
; CHECK: # %bb.0:
5835-
; CHECK-NEXT: li a0, 2000
5836-
; CHECK-NEXT: vsetivli zero, 8, e16, m1, ta, mu
5837-
; CHECK-NEXT: vmsgtu.vx v0, v8, a0
58385831
; CHECK-NEXT: li a0, -2001
5839-
; CHECK-NEXT: vadd.vx v8, v8, a0, v0.t
5832+
; CHECK-NEXT: vsetivli zero, 8, e16, m1, ta, ma
5833+
; CHECK-NEXT: vadd.vx v9, v8, a0
5834+
; CHECK-NEXT: vminu.vv v8, v9, v8
58405835
; CHECK-NEXT: ret
58415836
%cmp = icmp ugt <8 x i16> %x, splat (i16 2000)
58425837
%sub = add <8 x i16> %x, splat (i16 -2001)
@@ -5847,13 +5842,11 @@ define <8 x i16> @sub_if_uge_C_v8i16(<8 x i16> %x) {
58475842
define <4 x i32> @sub_if_uge_C_v4i32(<4 x i32> %x) {
58485843
; CHECK-LABEL: sub_if_uge_C_v4i32:
58495844
; CHECK: # %bb.0:
5850-
; CHECK-NEXT: lui a0, 16
5851-
; CHECK-NEXT: addi a0, a0, -16
5852-
; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, mu
5853-
; CHECK-NEXT: vmsgtu.vx v0, v8, a0
58545845
; CHECK-NEXT: lui a0, 1048560
58555846
; CHECK-NEXT: addi a0, a0, 15
5856-
; CHECK-NEXT: vadd.vx v8, v8, a0, v0.t
5847+
; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, ma
5848+
; CHECK-NEXT: vadd.vx v9, v8, a0
5849+
; CHECK-NEXT: vminu.vv v8, v9, v8
58575850
; CHECK-NEXT: ret
58585851
%cmp = icmp ugt <4 x i32> %x, splat (i32 65520)
58595852
%sub = add <4 x i32> %x, splat (i32 -65521)
@@ -5864,14 +5857,11 @@ define <4 x i32> @sub_if_uge_C_v4i32(<4 x i32> %x) {
58645857
define <4 x i32> @sub_if_uge_C_swapped_v4i32(<4 x i32> %x) {
58655858
; CHECK-LABEL: sub_if_uge_C_swapped_v4i32:
58665859
; CHECK: # %bb.0:
5867-
; CHECK-NEXT: lui a0, 16
5868-
; CHECK-NEXT: addi a0, a0, -15
5869-
; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, ma
5870-
; CHECK-NEXT: vmsltu.vx v0, v8, a0
58715860
; CHECK-NEXT: lui a0, 1048560
58725861
; CHECK-NEXT: addi a0, a0, 15
5862+
; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, ma
58735863
; CHECK-NEXT: vadd.vx v9, v8, a0
5874-
; CHECK-NEXT: vmerge.vvm v8, v9, v8, v0
5864+
; CHECK-NEXT: vminu.vv v8, v8, v9
58755865
; CHECK-NEXT: ret
58765866
%cmp = icmp ult <4 x i32> %x, splat (i32 65521)
58775867
%sub = add <4 x i32> %x, splat (i32 -65521)
@@ -5883,38 +5873,28 @@ define <2 x i64> @sub_if_uge_C_v2i64(<2 x i64> %x) nounwind {
58835873
; RV32-LABEL: sub_if_uge_C_v2i64:
58845874
; RV32: # %bb.0:
58855875
; RV32-NEXT: addi sp, sp, -16
5886-
; RV32-NEXT: li a0, 1
5887-
; RV32-NEXT: lui a1, 172127
5888-
; RV32-NEXT: mv a2, sp
5889-
; RV32-NEXT: addi a1, a1, 512
5890-
; RV32-NEXT: sw a1, 0(sp)
5891-
; RV32-NEXT: sw a0, 4(sp)
58925876
; RV32-NEXT: li a0, -2
5893-
; RV32-NEXT: vsetivli zero, 2, e64, m1, ta, mu
5894-
; RV32-NEXT: vlse64.v v9, (a2), zero
58955877
; RV32-NEXT: lui a1, 876449
58965878
; RV32-NEXT: addi a1, a1, -513
58975879
; RV32-NEXT: sw a1, 8(sp)
58985880
; RV32-NEXT: sw a0, 12(sp)
58995881
; RV32-NEXT: addi a0, sp, 8
5900-
; RV32-NEXT: vlse64.v v10, (a0), zero
5901-
; RV32-NEXT: vmsltu.vv v0, v9, v8
5902-
; RV32-NEXT: vadd.vv v8, v8, v10, v0.t
5882+
; RV32-NEXT: vsetivli zero, 2, e64, m1, ta, ma
5883+
; RV32-NEXT: vlse64.v v9, (a0), zero
5884+
; RV32-NEXT: vadd.vv v9, v8, v9
5885+
; RV32-NEXT: vminu.vv v8, v9, v8
59035886
; RV32-NEXT: addi sp, sp, 16
59045887
; RV32-NEXT: ret
59055888
;
59065889
; RV64-LABEL: sub_if_uge_C_v2i64:
59075890
; RV64: # %bb.0:
5908-
; RV64-NEXT: lui a0, 2384
5909-
; RV64-NEXT: addi a0, a0, 761
5910-
; RV64-NEXT: slli a0, a0, 9
5911-
; RV64-NEXT: vsetivli zero, 2, e64, m1, ta, mu
5912-
; RV64-NEXT: vmsgtu.vx v0, v8, a0
59135891
; RV64-NEXT: lui a0, 1048278
59145892
; RV64-NEXT: addi a0, a0, -95
59155893
; RV64-NEXT: slli a0, a0, 12
59165894
; RV64-NEXT: addi a0, a0, -513
5917-
; RV64-NEXT: vadd.vx v8, v8, a0, v0.t
5895+
; RV64-NEXT: vsetivli zero, 2, e64, m1, ta, ma
5896+
; RV64-NEXT: vadd.vx v9, v8, a0
5897+
; RV64-NEXT: vminu.vv v8, v9, v8
59185898
; RV64-NEXT: ret
59195899
%cmp = icmp ugt <2 x i64> %x, splat (i64 5000000000)
59205900
%sub = add <2 x i64> %x, splat (i64 -5000000001)

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