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[LLVM] Port SVE tests in llvm/test/CodeGen/AArch64 to use splat()
This is preparation work towards making such splats use Constant{Int,FP} by default for scalable vectors.
1 parent d0d12fc commit 9fd7523

37 files changed

+1051
-2650
lines changed

‎llvm/test/CodeGen/AArch64/DAGCombine_vscale.ll‎

Lines changed: 9 additions & 23 deletions
Original file line numberDiff line numberDiff line change
@@ -10,10 +10,8 @@ define <vscale x 4 x i32> @sext_inreg(<vscale x 4 x i32> %a) {
1010
; CHECK-NEXT: ptrue p0.s
1111
; CHECK-NEXT: sxth z0.s, p0/m, z0.s
1212
; CHECK-NEXT: ret
13-
%in = insertelement <vscale x 4 x i32> undef, i32 16, i32 0
14-
%splat = shufflevector <vscale x 4 x i32> %in, <vscale x 4 x i32> undef, <vscale x 4 x i32> zeroinitializer
15-
%sext = shl <vscale x 4 x i32> %a, %splat
16-
%conv = ashr <vscale x 4 x i32> %sext, %splat
13+
%sext = shl <vscale x 4 x i32> %a, splat(i32 16)
14+
%conv = ashr <vscale x 4 x i32> %sext, splat(i32 16)
1715
ret <vscale x 4 x i32> %conv
1816
}
1917

@@ -23,12 +21,8 @@ define <vscale x 4 x i32> @ashr_shl(<vscale x 4 x i32> %a) {
2321
; CHECK-NEXT: lsl z0.s, z0.s, #8
2422
; CHECK-NEXT: asr z0.s, z0.s, #16
2523
; CHECK-NEXT: ret
26-
%in1 = insertelement <vscale x 4 x i32> undef, i32 8, i32 0
27-
%splat1 = shufflevector <vscale x 4 x i32> %in1, <vscale x 4 x i32> undef, <vscale x 4 x i32> zeroinitializer
28-
%in2 = insertelement <vscale x 4 x i32> undef, i32 16, i32 0
29-
%splat2 = shufflevector <vscale x 4 x i32> %in2, <vscale x 4 x i32> undef, <vscale x 4 x i32> zeroinitializer
30-
%shl = shl <vscale x 4 x i32> %a, %splat1
31-
%r = ashr <vscale x 4 x i32> %shl, %splat2
24+
%shl = shl <vscale x 4 x i32> %a, splat(i32 8)
25+
%r = ashr <vscale x 4 x i32> %shl, splat(i32 16)
3226
ret <vscale x 4 x i32> %r
3327
}
3428

@@ -38,12 +32,8 @@ define <vscale x 4 x i32> @ashr_shl_illegal_trunc_vec_ty(<vscale x 4 x i32> %a)
3832
; CHECK-NEXT: lsl z0.s, z0.s, #8
3933
; CHECK-NEXT: asr z0.s, z0.s, #11
4034
; CHECK-NEXT: ret
41-
%in1 = insertelement <vscale x 4 x i32> undef, i32 8, i32 0
42-
%splat1 = shufflevector <vscale x 4 x i32> %in1, <vscale x 4 x i32> undef, <vscale x 4 x i32> zeroinitializer
43-
%in2 = insertelement <vscale x 4 x i32> undef, i32 11, i32 0
44-
%splat2 = shufflevector <vscale x 4 x i32> %in2, <vscale x 4 x i32> undef, <vscale x 4 x i32> zeroinitializer
45-
%shl = shl <vscale x 4 x i32> %a, %splat1
46-
%r = ashr <vscale x 4 x i32> %shl, %splat2
35+
%shl = shl <vscale x 4 x i32> %a, splat(i32 8)
36+
%r = ashr <vscale x 4 x i32> %shl, splat(i32 11)
4737
ret <vscale x 4 x i32> %r
4838
}
4939

@@ -55,12 +45,8 @@ define <vscale x 4 x i32> @ashr_add_shl_nxv4i8(<vscale x 4 x i32> %a) {
5545
; CHECK-NEXT: add z0.s, z0.s, z1.s
5646
; CHECK-NEXT: asr z0.s, z0.s, #24
5747
; CHECK-NEXT: ret
58-
%in1 = insertelement <vscale x 4 x i32> undef, i32 24, i32 0
59-
%splat1 = shufflevector <vscale x 4 x i32> %in1, <vscale x 4 x i32> undef, <vscale x 4 x i32> zeroinitializer
60-
%in2 = insertelement <vscale x 4 x i32> undef, i32 16777216, i32 0
61-
%splat2 = shufflevector <vscale x 4 x i32> %in2, <vscale x 4 x i32> undef, <vscale x 4 x i32> zeroinitializer
62-
%conv = shl <vscale x 4 x i32> %a, %splat1
63-
%sext = add <vscale x 4 x i32> %conv, %splat2
64-
%conv1 = ashr <vscale x 4 x i32> %sext, %splat1
48+
%conv = shl <vscale x 4 x i32> %a, splat(i32 24)
49+
%sext = add <vscale x 4 x i32> %conv, splat(i32 16777216)
50+
%conv1 = ashr <vscale x 4 x i32> %sext, splat(i32 24)
6551
ret <vscale x 4 x i32> %conv1
6652
}

‎llvm/test/CodeGen/AArch64/llvm-ir-to-intrinsic.ll‎

Lines changed: 1 addition & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -1165,9 +1165,7 @@ define <vscale x 2 x i64> @fshl_rot_const_i64(<vscale x 2 x i64> %a){
11651165
; CHECK-NEXT: lsl z0.d, z0.d, #3
11661166
; CHECK-NEXT: orr z0.d, z0.d, z1.d
11671167
; CHECK-NEXT: ret
1168-
%insert = insertelement <vscale x 2 x i64> poison, i64 3, i32 0
1169-
%shuf = shufflevector <vscale x 2 x i64> %insert, <vscale x 2 x i64> poison, <vscale x 2 x i32> zeroinitializer
1170-
%fshl = call <vscale x 2 x i64> @llvm.fshl.nxv2i64(<vscale x 2 x i64> %a, <vscale x 2 x i64> %a, <vscale x 2 x i64> %shuf)
1168+
%fshl = call <vscale x 2 x i64> @llvm.fshl.nxv2i64(<vscale x 2 x i64> %a, <vscale x 2 x i64> %a, <vscale x 2 x i64> splat(i64 3))
11711169
ret <vscale x 2 x i64> %fshl
11721170
}
11731171

‎llvm/test/CodeGen/AArch64/sme-disable-rematerialize-with-streaming-mode-changes.ll‎

Lines changed: 1 addition & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -54,9 +54,7 @@ entry:
5454
for.body: ; preds = %entry, %for.body
5555
%index.03 = phi i32 [ %inc, %for.body ], [ 0, %entry ]
5656
call void asm sideeffect "", "~{x19},~{x20},~{x21},~{x22},~{x23},~{x24},~{x25},~{x26},~{x27}"() nounwind
57-
%ptrue.ins = insertelement <vscale x 16 x i1> poison, i1 1, i32 0
58-
%ptrue = shufflevector <vscale x 16 x i1> %ptrue.ins, <vscale x 16 x i1> poison, <vscale x 16 x i32> zeroinitializer
59-
call void @bar(<vscale x 16 x i1> %ptrue)
57+
call void @bar(<vscale x 16 x i1> splat(i1 true))
6058
%inc = add nuw nsw i32 %index.03, 1
6159
%exitcond.not = icmp eq i32 %inc, %N
6260
br i1 %exitcond.not, label %for.cond.cleanup, label %for.body

‎llvm/test/CodeGen/AArch64/sve-adr.ll‎

Lines changed: 6 additions & 12 deletions
Original file line numberDiff line numberDiff line change
@@ -14,10 +14,8 @@ define <vscale x 4 x i32> @adr_32bit_lsl1(<vscale x 4 x i32> %base, <vscale x
1414
; CHECK: // %bb.0:
1515
; CHECK-NEXT: adr z0.s, [z0.s, z1.s, lsl #1]
1616
; CHECK-NEXT: ret
17-
%splat_insert = insertelement <vscale x 4 x i32> poison, i32 1, i32 0
18-
%one = shufflevector <vscale x 4 x i32> %splat_insert, <vscale x 4 x i32> poison, <vscale x 4 x i32> zeroinitializer
19-
%shiftedOffset = shl <vscale x 4 x i32> %idx, %one
20-
%address = add <vscale x 4 x i32> %base, %shiftedOffset
17+
%offset = shl <vscale x 4 x i32> %idx, splat (i32 1)
18+
%address = add <vscale x 4 x i32> %base, %offset
2119
ret <vscale x 4 x i32> %address
2220
}
2321

@@ -26,10 +24,8 @@ define <vscale x 4 x i32> @adr_32bit_lsl2(<vscale x 4 x i32> %base, <vscale x
2624
; CHECK: // %bb.0:
2725
; CHECK-NEXT: adr z0.s, [z0.s, z1.s, lsl #2]
2826
; CHECK-NEXT: ret
29-
%splat_insert = insertelement <vscale x 4 x i32> poison, i32 2, i32 0
30-
%two = shufflevector <vscale x 4 x i32> %splat_insert, <vscale x 4 x i32> poison, <vscale x 4 x i32> zeroinitializer
31-
%shiftedOffset = shl <vscale x 4 x i32> %idx, %two
32-
%address = add <vscale x 4 x i32> %base, %shiftedOffset
27+
%offset = shl <vscale x 4 x i32> %idx, splat (i32 2)
28+
%address = add <vscale x 4 x i32> %base, %offset
3329
ret <vscale x 4 x i32> %address
3430
}
3531

@@ -38,10 +34,8 @@ define <vscale x 4 x i32> @adr_32bit_lsl3(<vscale x 4 x i32> %base, <vscale x
3834
; CHECK: // %bb.0:
3935
; CHECK-NEXT: adr z0.s, [z0.s, z1.s, lsl #3]
4036
; CHECK-NEXT: ret
41-
%splat_insert = insertelement <vscale x 4 x i32> poison, i32 3, i32 0
42-
%three = shufflevector <vscale x 4 x i32> %splat_insert, <vscale x 4 x i32> poison, <vscale x 4 x i32> zeroinitializer
43-
%shiftedOffset = shl <vscale x 4 x i32> %idx, %three
44-
%address = add <vscale x 4 x i32> %base, %shiftedOffset
37+
%offset = shl <vscale x 4 x i32> %idx, splat (i32 3)
38+
%address = add <vscale x 4 x i32> %base, %offset
4539
ret <vscale x 4 x i32> %address
4640
}
4741

‎llvm/test/CodeGen/AArch64/sve-cmp-folds.ll‎

Lines changed: 4 additions & 12 deletions
Original file line numberDiff line numberDiff line change
@@ -8,9 +8,7 @@ define <vscale x 8 x i1> @not_icmp_sle_nxv8i16(<vscale x 8 x i16> %a, <vscale x
88
; CHECK-NEXT: cmpgt p0.h, p0/z, z0.h, z1.h
99
; CHECK-NEXT: ret
1010
%icmp = icmp sle <vscale x 8 x i16> %a, %b
11-
%tmp = insertelement <vscale x 8 x i1> undef, i1 true, i32 0
12-
%ones = shufflevector <vscale x 8 x i1> %tmp, <vscale x 8 x i1> undef, <vscale x 8 x i32> zeroinitializer
13-
%not = xor <vscale x 8 x i1> %ones, %icmp
11+
%not = xor <vscale x 8 x i1> splat(i1 true), %icmp
1412
ret <vscale x 8 x i1> %not
1513
}
1614

@@ -21,9 +19,7 @@ define <vscale x 4 x i1> @not_icmp_sgt_nxv4i32(<vscale x 4 x i32> %a, <vscale x
2119
; CHECK-NEXT: cmpge p0.s, p0/z, z1.s, z0.s
2220
; CHECK-NEXT: ret
2321
%icmp = icmp sgt <vscale x 4 x i32> %a, %b
24-
%tmp = insertelement <vscale x 4 x i1> undef, i1 true, i32 0
25-
%ones = shufflevector <vscale x 4 x i1> %tmp, <vscale x 4 x i1> undef, <vscale x 4 x i32> zeroinitializer
26-
%not = xor <vscale x 4 x i1> %icmp, %ones
22+
%not = xor <vscale x 4 x i1> %icmp, splat(i1 true)
2723
ret <vscale x 4 x i1> %not
2824
}
2925

@@ -34,9 +30,7 @@ define <vscale x 2 x i1> @not_fcmp_une_nxv2f64(<vscale x 2 x double> %a, <vscale
3430
; CHECK-NEXT: fcmeq p0.d, p0/z, z0.d, z1.d
3531
; CHECK-NEXT: ret
3632
%icmp = fcmp une <vscale x 2 x double> %a, %b
37-
%tmp = insertelement <vscale x 2 x i1> undef, i1 true, i32 0
38-
%ones = shufflevector <vscale x 2 x i1> %tmp, <vscale x 2 x i1> undef, <vscale x 2 x i32> zeroinitializer
39-
%not = xor <vscale x 2 x i1> %icmp, %ones
33+
%not = xor <vscale x 2 x i1> %icmp, splat(i1 true)
4034
ret <vscale x 2 x i1> %not
4135
}
4236

@@ -47,9 +41,7 @@ define <vscale x 4 x i1> @not_fcmp_uge_nxv4f32(<vscale x 4 x float> %a, <vscale
4741
; CHECK-NEXT: fcmgt p0.s, p0/z, z1.s, z0.s
4842
; CHECK-NEXT: ret
4943
%icmp = fcmp uge <vscale x 4 x float> %a, %b
50-
%tmp = insertelement <vscale x 4 x i1> undef, i1 true, i32 0
51-
%ones = shufflevector <vscale x 4 x i1> %tmp, <vscale x 4 x i1> undef, <vscale x 4 x i32> zeroinitializer
52-
%not = xor <vscale x 4 x i1> %icmp, %ones
44+
%not = xor <vscale x 4 x i1> %icmp, splat(i1 true)
5345
ret <vscale x 4 x i1> %not
5446
}
5547

‎llvm/test/CodeGen/AArch64/sve-dead-masked-store.ll‎

Lines changed: 3 additions & 9 deletions
Original file line numberDiff line numberDiff line change
@@ -17,10 +17,8 @@ define void @dead_masked_store_alltrue_same(<vscale x 4 x i32> %val, ptr %a, <vs
1717
; CHECK-NEXT: ptrue p0.s
1818
; CHECK-NEXT: st1w { z0.s }, p0, [x0]
1919
; CHECK-NEXT: ret
20-
%alltrue.ins = insertelement <vscale x 4 x i1> poison, i1 true, i32 0
21-
%alltrue = shufflevector <vscale x 4 x i1> %alltrue.ins, <vscale x 4 x i1> poison, <vscale x 4 x i32> zeroinitializer
2220
call void @llvm.masked.store.nxv4i32(<vscale x 4 x i32> %val, ptr %a, i32 4, <vscale x 4 x i1> %mask)
23-
call void @llvm.masked.store.nxv4i32(<vscale x 4 x i32> %val, ptr %a, i32 4, <vscale x 4 x i1> %alltrue)
21+
call void @llvm.masked.store.nxv4i32(<vscale x 4 x i32> %val, ptr %a, i32 4, <vscale x 4 x i1> splat(i1 true))
2422
ret void
2523
}
2624

@@ -30,10 +28,8 @@ define void @dead_masked_store_alltrue_bigger(<vscale x 4 x i16> %val, <vscale x
3028
; CHECK-NEXT: ptrue p0.s
3129
; CHECK-NEXT: st1w { z1.s }, p0, [x0]
3230
; CHECK-NEXT: ret
33-
%alltrue.ins = insertelement <vscale x 4 x i1> poison, i1 true, i32 0
34-
%alltrue = shufflevector <vscale x 4 x i1> %alltrue.ins, <vscale x 4 x i1> poison, <vscale x 4 x i32> zeroinitializer
3531
call void @llvm.masked.store.nxv4i16(<vscale x 4 x i16> %val, ptr %a, i32 4, <vscale x 4 x i1> %mask)
36-
call void @llvm.masked.store.nxv4i32(<vscale x 4 x i32> %val1, ptr %a, i32 4, <vscale x 4 x i1> %alltrue)
32+
call void @llvm.masked.store.nxv4i32(<vscale x 4 x i32> %val1, ptr %a, i32 4, <vscale x 4 x i1> splat(i1 true))
3733
ret void
3834
}
3935

@@ -44,10 +40,8 @@ define void @dead_masked_store_alltrue_smaller(<vscale x 4 x i32> %val, <vscale
4440
; CHECK-NEXT: st1w { z0.s }, p0, [x0]
4541
; CHECK-NEXT: st1h { z1.s }, p1, [x0]
4642
; CHECK-NEXT: ret
47-
%alltrue.ins = insertelement <vscale x 4 x i1> poison, i1 true, i32 0
48-
%alltrue = shufflevector <vscale x 4 x i1> %alltrue.ins, <vscale x 4 x i1> poison, <vscale x 4 x i32> zeroinitializer
4943
call void @llvm.masked.store.nxv4i32(<vscale x 4 x i32> %val, ptr %a, i32 4, <vscale x 4 x i1> %mask)
50-
call void @llvm.masked.store.nxv4i16(<vscale x 4 x i16> %val1, ptr %a, i32 4, <vscale x 4 x i1> %alltrue)
44+
call void @llvm.masked.store.nxv4i16(<vscale x 4 x i16> %val1, ptr %a, i32 4, <vscale x 4 x i1> splat(i1 true))
5145
ret void
5246
}
5347

‎llvm/test/CodeGen/AArch64/sve-extract-fixed-vector.ll‎

Lines changed: 2 additions & 6 deletions
Original file line numberDiff line numberDiff line change
@@ -392,9 +392,7 @@ define <2 x float> @extract_v2f32_nxv4f32_splat_const() {
392392
; CHECK: // %bb.0:
393393
; CHECK-NEXT: fmov v0.2s, #1.00000000
394394
; CHECK-NEXT: ret
395-
%ins = insertelement <vscale x 4 x float> poison, float 1.0, i32 0
396-
%splat = shufflevector <vscale x 4 x float> %ins, <vscale x 4 x float> poison, <vscale x 4 x i32> zeroinitializer
397-
%ext = call <2 x float> @llvm.vector.extract.v2f32.nxv4f32(<vscale x 4 x float> %splat, i64 0)
395+
%ext = call <2 x float> @llvm.vector.extract.v2f32.nxv4f32(<vscale x 4 x float> splat(float 1.0), i64 0)
398396
ret <2 x float> %ext
399397
}
400398

@@ -403,9 +401,7 @@ define <4 x i32> @extract_v4i32_nxv8i32_splat_const() {
403401
; CHECK: // %bb.0:
404402
; CHECK-NEXT: movi v0.4s, #1
405403
; CHECK-NEXT: ret
406-
%ins = insertelement <vscale x 8 x i32> poison, i32 1, i32 0
407-
%splat = shufflevector <vscale x 8 x i32> %ins, <vscale x 8 x i32> poison, <vscale x 8 x i32> zeroinitializer
408-
%ext = call <4 x i32> @llvm.vector.extract.v4i32.nxv8i32(<vscale x 8 x i32> %splat, i64 0)
404+
%ext = call <4 x i32> @llvm.vector.extract.v4i32.nxv8i32(<vscale x 8 x i32> splat(i32 1), i64 0)
409405
ret <4 x i32> %ext
410406
}
411407

‎llvm/test/CodeGen/AArch64/sve-extract-scalable-vector.ll‎

Lines changed: 3 additions & 9 deletions
Original file line numberDiff line numberDiff line change
@@ -1039,9 +1039,7 @@ define <vscale x 2 x float> @extract_nxv2f32_nxv4f32_splat_const() {
10391039
; CHECK: // %bb.0:
10401040
; CHECK-NEXT: fmov z0.s, #1.00000000
10411041
; CHECK-NEXT: ret
1042-
%ins = insertelement <vscale x 4 x float> poison, float 1.0, i32 0
1043-
%splat = shufflevector <vscale x 4 x float> %ins, <vscale x 4 x float> poison, <vscale x 4 x i32> zeroinitializer
1044-
%ext = call <vscale x 2 x float> @llvm.vector.extract.nxv2f32.nxv4f32(<vscale x 4 x float> %splat, i64 0)
1042+
%ext = call <vscale x 2 x float> @llvm.vector.extract.nxv2f32.nxv4f32(<vscale x 4 x float> splat(float 1.0), i64 0)
10451043
ret <vscale x 2 x float> %ext
10461044
}
10471045

@@ -1050,9 +1048,7 @@ define <vscale x 4 x i32> @extract_nxv4i32_nxv8i32_splat_const() {
10501048
; CHECK: // %bb.0:
10511049
; CHECK-NEXT: mov z0.s, #1 // =0x1
10521050
; CHECK-NEXT: ret
1053-
%ins = insertelement <vscale x 8 x i32> poison, i32 1, i32 0
1054-
%splat = shufflevector <vscale x 8 x i32> %ins, <vscale x 8 x i32> poison, <vscale x 8 x i32> zeroinitializer
1055-
%ext = call <vscale x 4 x i32> @llvm.vector.extract.nxv4i32.nxv8i32(<vscale x 8 x i32> %splat, i64 0)
1051+
%ext = call <vscale x 4 x i32> @llvm.vector.extract.nxv4i32.nxv8i32(<vscale x 8 x i32> splat(i32 1), i64 0)
10561052
ret <vscale x 4 x i32> %ext
10571053
}
10581054

@@ -1061,9 +1057,7 @@ define <vscale x 2 x i1> @extract_nxv2i1_nxv16i1_all_ones() {
10611057
; CHECK: // %bb.0:
10621058
; CHECK-NEXT: ptrue p0.d
10631059
; CHECK-NEXT: ret
1064-
%ins = insertelement <vscale x 16 x i1> poison, i1 1, i32 0
1065-
%splat = shufflevector <vscale x 16 x i1> %ins, <vscale x 16 x i1> poison, <vscale x 16 x i32> zeroinitializer
1066-
%ext = call <vscale x 2 x i1> @llvm.vector.extract.nxv2i1.nxv16i1(<vscale x 16 x i1> %splat, i64 0)
1060+
%ext = call <vscale x 2 x i1> @llvm.vector.extract.nxv2i1.nxv16i1(<vscale x 16 x i1> splat(i1 true), i64 0)
10671061
ret <vscale x 2 x i1> %ext
10681062
}
10691063

‎llvm/test/CodeGen/AArch64/sve-fadda-select.ll‎

Lines changed: 6 additions & 18 deletions
Original file line numberDiff line numberDiff line change
@@ -10,9 +10,7 @@ define float @pred_fadda_nxv2f32(float %x, <vscale x 2 x float> %y, <vscale x 2
1010
; CHECK-NEXT: fadda s0, p0, s0, z1.s
1111
; CHECK-NEXT: // kill: def $s0 killed $s0 killed $z0
1212
; CHECK-NEXT: ret
13-
%i = insertelement <vscale x 2 x float> poison, float -0.000000e+00, i32 0
14-
%minus0 = shufflevector <vscale x 2 x float> %i, <vscale x 2 x float> poison, <vscale x 2 x i32> zeroinitializer
15-
%sel = select <vscale x 2 x i1> %mask, <vscale x 2 x float> %y, <vscale x 2 x float> %minus0
13+
%sel = select <vscale x 2 x i1> %mask, <vscale x 2 x float> %y, <vscale x 2 x float> splat(float -0.000000e+00)
1614
%fadda = call float @llvm.vector.reduce.fadd.nxv2f32(float %x, <vscale x 2 x float> %sel)
1715
ret float %fadda
1816
}
@@ -24,9 +22,7 @@ define float @pred_fadda_nxv4f32(float %x, <vscale x 4 x float> %y, <vscale x 4
2422
; CHECK-NEXT: fadda s0, p0, s0, z1.s
2523
; CHECK-NEXT: // kill: def $s0 killed $s0 killed $z0
2624
; CHECK-NEXT: ret
27-
%i = insertelement <vscale x 4 x float> poison, float -0.000000e+00, i32 0
28-
%minus0 = shufflevector <vscale x 4 x float> %i, <vscale x 4 x float> poison, <vscale x 4 x i32> zeroinitializer
29-
%sel = select <vscale x 4 x i1> %mask, <vscale x 4 x float> %y, <vscale x 4 x float> %minus0
25+
%sel = select <vscale x 4 x i1> %mask, <vscale x 4 x float> %y, <vscale x 4 x float> splat(float -0.000000e+00)
3026
%fadda = call float @llvm.vector.reduce.fadd.nxv4f32(float %x, <vscale x 4 x float> %sel)
3127
ret float %fadda
3228
}
@@ -38,9 +34,7 @@ define double @pred_fadda_nxv2f64(double %x, <vscale x 2 x double> %y, <vscale x
3834
; CHECK-NEXT: fadda d0, p0, d0, z1.d
3935
; CHECK-NEXT: // kill: def $d0 killed $d0 killed $z0
4036
; CHECK-NEXT: ret
41-
%i = insertelement <vscale x 2 x double> poison, double -0.000000e+00, i32 0
42-
%minus0 = shufflevector <vscale x 2 x double> %i, <vscale x 2 x double> poison, <vscale x 2 x i32> zeroinitializer
43-
%sel = select <vscale x 2 x i1> %mask, <vscale x 2 x double> %y, <vscale x 2 x double> %minus0
37+
%sel = select <vscale x 2 x i1> %mask, <vscale x 2 x double> %y, <vscale x 2 x double> splat(double -0.000000e+00)
4438
%fadda = call double @llvm.vector.reduce.fadd.nxv2f64(double %x, <vscale x 2 x double> %sel)
4539
ret double %fadda
4640
}
@@ -52,9 +46,7 @@ define half @pred_fadda_nxv2f16(half %x, <vscale x 2 x half> %y, <vscale x 2 x i
5246
; CHECK-NEXT: fadda h0, p0, h0, z1.h
5347
; CHECK-NEXT: // kill: def $h0 killed $h0 killed $z0
5448
; CHECK-NEXT: ret
55-
%i = insertelement <vscale x 2 x half> poison, half -0.000000e+00, i32 0
56-
%minus0 = shufflevector <vscale x 2 x half> %i, <vscale x 2 x half> poison, <vscale x 2 x i32> zeroinitializer
57-
%sel = select <vscale x 2 x i1> %mask, <vscale x 2 x half> %y, <vscale x 2 x half> %minus0
49+
%sel = select <vscale x 2 x i1> %mask, <vscale x 2 x half> %y, <vscale x 2 x half> splat(half -0.000000e+00)
5850
%fadda = call half @llvm.vector.reduce.fadd.nxv2f16(half %x, <vscale x 2 x half> %sel)
5951
ret half %fadda
6052
}
@@ -66,9 +58,7 @@ define half @pred_fadda_nxv4f16(half %x, <vscale x 4 x half> %y, <vscale x 4 x i
6658
; CHECK-NEXT: fadda h0, p0, h0, z1.h
6759
; CHECK-NEXT: // kill: def $h0 killed $h0 killed $z0
6860
; CHECK-NEXT: ret
69-
%i = insertelement <vscale x 4 x half> poison, half -0.000000e+00, i32 0
70-
%minus0 = shufflevector <vscale x 4 x half> %i, <vscale x 4 x half> poison, <vscale x 4 x i32> zeroinitializer
71-
%sel = select <vscale x 4 x i1> %mask, <vscale x 4 x half> %y, <vscale x 4 x half> %minus0
61+
%sel = select <vscale x 4 x i1> %mask, <vscale x 4 x half> %y, <vscale x 4 x half> splat(half -0.000000e+00)
7262
%fadda = call half @llvm.vector.reduce.fadd.nxv4f16(half %x, <vscale x 4 x half> %sel)
7363
ret half %fadda
7464
}
@@ -80,9 +70,7 @@ define half @pred_fadda_nxv8f16(half %x, <vscale x 8 x half> %y, <vscale x 8 x i
8070
; CHECK-NEXT: fadda h0, p0, h0, z1.h
8171
; CHECK-NEXT: // kill: def $h0 killed $h0 killed $z0
8272
; CHECK-NEXT: ret
83-
%i = insertelement <vscale x 8 x half> poison, half -0.000000e+00, i32 0
84-
%minus0 = shufflevector <vscale x 8 x half> %i, <vscale x 8 x half> poison, <vscale x 8 x i32> zeroinitializer
85-
%sel = select <vscale x 8 x i1> %mask, <vscale x 8 x half> %y, <vscale x 8 x half> %minus0
73+
%sel = select <vscale x 8 x i1> %mask, <vscale x 8 x half> %y, <vscale x 8 x half> splat(half -0.000000e+00)
8674
%fadda = call half @llvm.vector.reduce.fadd.nxv8f16(half %x, <vscale x 8 x half> %sel)
8775
ret half %fadda
8876
}

‎llvm/test/CodeGen/AArch64/sve-fold-loadext-and-splat-vector.ll‎

Lines changed: 1 addition & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -13,9 +13,7 @@ define <vscale x 2 x i64> @fold_loadext_and(ptr %ptr, i32 %needle, <vscale x 2 x
1313
; CHECK-NEXT: ret
1414
%load = load <vscale x 2 x i32>, ptr %ptr, align 4
1515
%ext = zext <vscale x 2 x i32> %load to <vscale x 2 x i64>
16-
%splatinsert = insertelement <vscale x 2 x i64> poison, i64 4294967295, i64 0
17-
%splat = shufflevector <vscale x 2 x i64> %splatinsert, <vscale x 2 x i64> poison, <vscale x 2 x i32> zeroinitializer
18-
%and = and <vscale x 2 x i64> %ext, %splat
16+
%and = and <vscale x 2 x i64> %ext, splat(i64 4294967295)
1917
ret <vscale x 2 x i64> %and
2018
}
2119

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