Merge branch 'main' into x86-pmullw-vXi8

Author: RKSimon

clang/test/CodeGen/builtins.c

@@ -1289,7 +1289,10 @@ void test_builtin_ctzg(unsigned char uc, unsigned short us, unsigned int ui,
 // CHECK-LABEL: define{{.*}} void @test_builtin_bswapg
 void test_builtin_bswapg(unsigned char uc, unsigned short us, unsigned int ui,
                        unsigned long ul, unsigned long long ull,
-                       unsigned __int128 ui128, _BitInt(8) bi8,
+#ifdef __SIZEOF_INT128__
+                       unsigned __int128 ui128,
+#endif
+                       _BitInt(8) bi8,
                        _BitInt(16) bi16, _BitInt(32) bi32, 
                        _BitInt(64) bi64, _BitInt(128) bi128) {
   uc = __builtin_bswapg(uc);
@@ -1303,8 +1306,10 @@ void test_builtin_bswapg(unsigned char uc, unsigned short us, unsigned int ui,
   // CHECK: call i64 @llvm.bswap.i64
   ull = __builtin_bswapg(ull);
   // CHECK: call i64 @llvm.bswap.i64
+#ifdef __SIZEOF_INT128__
   ui128 = __builtin_bswapg(ui128);
   // CHECK: call i128 @llvm.bswap.i128
+#endif
   bi8 = __builtin_bswapg(bi8);
   // CHECK: %17 = load i8, ptr %bi8.addr, align 1
   // CHECK: store i8 %17, ptr %bi8.addr

libcxx/test/std/language.support/support.dynamic/hardware_inference_size.compile.pass.cpp

@@ -7,7 +7,6 @@
 //===----------------------------------------------------------------------===//
 
 // UNSUPPORTED: c++03, c++11, c++14
-// UNSUPPORTED: (clang || apple-clang) && stdlib=libc++
 
 #include <new>
 

llvm/test/CodeGen/AArch64/pr166870.ll

@@ -1,68 +1,99 @@
 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 6
 ; RUN: llc -O3 < %s -mtriple=aarch64 | FileCheck %s
 
-; The seemingly redundant mov where src_reg == dst_reg shouldn't be removed,
-; because it has the effect of zeroing the upper bits in x8.
+; The seemingly redundant wreg mov where src_reg == dst_reg shouldn't be
+; removed, because it has the effect of zeroing the upper bits in the matching
+; xreg.
 
-define i32 @ham(i32 %arg, i1 %arg1, i1 %arg2, ptr %arg3) nounwind {
-; CHECK-LABEL: ham:
+define i32 @widget(i32 %arg, i32 %arg1, i1 %arg2, ptr %arg3, i1 %arg4) #0 nounwind {
+; CHECK-LABEL: widget:
 ; CHECK:       // %bb.0: // %bb
-; CHECK-NEXT:    stp x30, x21, [sp, #-32]! // 16-byte Folded Spill
-; CHECK-NEXT:    stp x20, x19, [sp, #16] // 16-byte Folded Spill
-; CHECK-NEXT:    tbnz w1, #0, .LBB0_3
-; CHECK-NEXT:  // %bb.1: // %bb4
-; CHECK-NEXT:    tbnz w2, #0, .LBB0_3
-; CHECK-NEXT:  // %bb.2: // %bb5
-; CHECK-NEXT:    mov x19, x3
-; CHECK-NEXT:    mov w21, w1
-; CHECK-NEXT:    mov w20, w0
-; CHECK-NEXT:    bl zot
-; CHECK-NEXT:    tbz w21, #0, .LBB0_4
-; CHECK-NEXT:  .LBB0_3: // %bb6
-; CHECK-NEXT:    ldp x20, x19, [sp, #16] // 16-byte Folded Reload
-; CHECK-NEXT:    mov w0, wzr
-; CHECK-NEXT:    ldp x30, x21, [sp], #32 // 16-byte Folded Reload
+; CHECK-NEXT:    tbz w2, #0, .LBB0_2
+; CHECK-NEXT:  // %bb.1:
+; CHECK-NEXT:    mov w0, #1 // =0x1
+; CHECK-NEXT:    ret
+; CHECK-NEXT:  .LBB0_2: // %bb5
+; CHECK-NEXT:    tbz w4, #0, .LBB0_4
+; CHECK-NEXT:  // %bb.3:
+; CHECK-NEXT:    mov w0, #0 // =0x0
 ; CHECK-NEXT:    ret
-; CHECK-NEXT:  .LBB0_4:
-; CHECK-NEXT:    mov w8, w20
-; CHECK-NEXT:    mov w20, wzr
+; CHECK-NEXT:  .LBB0_4: // %bb6
+; CHECK-NEXT:    str x30, [sp, #-48]! // 8-byte Folded Spill
+; CHECK-NEXT:    stp x22, x21, [sp, #16] // 16-byte Folded Spill
+; CHECK-NEXT:    stp x20, x19, [sp, #32] // 16-byte Folded Spill
+; CHECK-NEXT:    mov x19, x3
+; CHECK-NEXT:    mov x20, x0
+; CHECK-NEXT:    mov x21, x1
+; CHECK-NEXT:    bl baz
+; CHECK-NEXT:    mov w0, #0 // =0x0
+; CHECK-NEXT:    cbnz wzr, .LBB0_11
+; CHECK-NEXT:  // %bb.5: // %bb6
+; CHECK-NEXT:    mov w10, #1 // =0x1
+; CHECK-NEXT:    cbnz w10, .LBB0_11
+; CHECK-NEXT:  // %bb.6: // %bb7
+; CHECK-NEXT:    cbnz w10, .LBB0_10
+; CHECK-NEXT:  // %bb.7: // %bb8
+; CHECK-NEXT:    mov x8, x21
+; CHECK-NEXT:    mov x9, x20
+; CHECK-NEXT:    mov w20, #0 // =0x0
+; CHECK-NEXT:    mov w9, w9
+; CHECK-NEXT:    mov x21, x9
 ; CHECK-NEXT:    mov w8, w8
-; CHECK-NEXT:    mov w21, w8
-; CHECK-NEXT:  .LBB0_5: // %bb7
+; CHECK-NEXT:    mov x22, x8
+; CHECK-NEXT:  .LBB0_8: // %bb10
 ; CHECK-NEXT:    // =>This Inner Loop Header: Depth=1
 ; CHECK-NEXT:    strb w20, [x19]
-; CHECK-NEXT:    cbnz x21, .LBB0_5
-; CHECK-NEXT:  // %bb.6: // %bb8
-; CHECK-NEXT:    // in Loop: Header=BB0_5 Depth=1
-; CHECK-NEXT:    bl quux
-; CHECK-NEXT:    b .LBB0_5
+; CHECK-NEXT:    cbnz x21, .LBB0_8
+; CHECK-NEXT:  // %bb.9: // %bb12
+; CHECK-NEXT:    // in Loop: Header=BB0_8 Depth=1
+; CHECK-NEXT:    bl snork
+; CHECK-NEXT:    cbnz x22, .LBB0_8
+; CHECK-NEXT:  .LBB0_10:
+; CHECK-NEXT:    mov w0, #0 // =0x0
+; CHECK-NEXT:  .LBB0_11:
+; CHECK-NEXT:    ldp x20, x19, [sp, #32] // 16-byte Folded Reload
+; CHECK-NEXT:    ldp x22, x21, [sp, #16] // 16-byte Folded Reload
+; CHECK-NEXT:    ldr x30, [sp], #48 // 8-byte Folded Reload
+; CHECK-NEXT:    ret
 bb:
-  br i1 %arg1, label %bb6, label %bb4
-
-bb4:
-  %load = load ptr, ptr null, align 8
-  br i1 %arg2, label %bb6, label %bb5
+  br i1 %arg2, label %bb14, label %bb5
 
 bb5:
-  %call = call i32 @zot() #0
-  %zext = zext i32 %arg to i64
-  br i1 %arg1, label %bb6, label %bb7
+  %load = load ptr, ptr null, align 8
+  br i1 %arg4, label %bb14, label %bb6
 
 bb6:
-  ret i32 0
+  %call = call i32 @baz() #1
+  %or = or i1 false, true
+  br i1 %or, label %bb14, label %bb7
 
 bb7:
-  store i8 0, ptr %arg3, align 1
-  %icmp = icmp eq i64 %zext, 0
-  br i1 %icmp, label %bb8, label %bb7
+  %icmp = icmp eq i32 0, 0
+  %zext = zext i32 %arg to i64
+  br i1 %icmp, label %bb14, label %bb8
 
 bb8:
-  call void @quux()
-  br label %bb7
+  %zext9 = zext i32 %arg1 to i64
+  br label %bb10
+
+bb10:
+  store i8 0, ptr %arg3, align 1
+  %icmp11 = icmp eq i64 %zext, 0
+  br i1 %icmp11, label %bb12, label %bb10
+
+bb12:
+  call void @snork()
+  %icmp13 = icmp eq i64 0, %zext9
+  br i1 %icmp13, label %bb14, label %bb10
+
+bb14:
+  %phi = phi i32 [ 0, %bb6 ], [ 0, %bb7 ], [ 0, %bb12 ], [ 1, %bb ], [ 0, %bb5 ]
+  ret i32 %phi
 }
 
-declare i32 @zot()
+declare i32 @baz()
 
-declare void @quux()
+declare void @snork()
 
-attributes #0 = { returns_twice }
+attributes #0 = { "target-cpu"="apple-m1" }
+attributes #1 = { returns_twice }

llvm/test/Transforms/LoopVectorize/vplan-printing.ll

@@ -329,8 +329,8 @@ for.end:
   ret void
 }
 
-define void @debug_loc_vpinstruction(ptr nocapture %asd, ptr nocapture %bsd) !dbg !5 {
-; CHECK-LABEL: Checking a loop in 'debug_loc_vpinstruction'
+define void @recipe_debug_loc_location(ptr nocapture %src) !dbg !5 {
+; CHECK-LABEL: Checking a loop in 'recipe_debug_loc_location'
 ; CHECK:    VPlan 'Initial VPlan for VF={4},UF>=1' {
 ; CHECK-NEXT: Live-in vp<[[VF:%.]]> = VF
 ; CHECK-NEXT: Live-in vp<[[VFxUF:%.]]> = VF * UF
@@ -347,14 +347,20 @@ define void @debug_loc_vpinstruction(ptr nocapture %asd, ptr nocapture %bsd) !db
 ; CHECK-NEXT:  vector.body:
 ; CHECK-NEXT:    EMIT vp<[[CAN_IV:%.+]]> = CANONICAL-INDUCTION ir<0>, vp<[[CAN_IV_NEXT:%.+]]>
 ; CHECK-NEXT:    vp<[[STEPS:%.+]]> = SCALAR-STEPS vp<[[CAN_IV]]>, ir<1>, vp<[[VF]]>
-; CHECK-NEXT:    CLONE ir<%isd> = getelementptr inbounds ir<%asd>, vp<[[STEPS]]>
+; CHECK-NEXT:    CLONE ir<%isd> = getelementptr inbounds ir<%src>, vp<[[STEPS]]>
+; CHECK-NOT:     !dbg
 ; CHECK-NEXT:    vp<[[VEC_PTR:%.+]]> = vector-pointer ir<%isd>
+; CHECK-NOT:     !dbg
 ; CHECK-NEXT:    WIDEN ir<%lsd> = load vp<[[VEC_PTR]]>
+; CHECK-NOT:     !dbg
 ; CHECK-NEXT:    WIDEN ir<%psd> = add nuw nsw ir<%lsd>, ir<23>
+; CHECK-NOT:     !dbg
 ; CHECK-NEXT:    WIDEN ir<%cmp1> = icmp slt ir<%lsd>, ir<100>
-; CHECK-NEXT:    EMIT vp<[[NOT1:%.+]]> = not ir<%cmp1>, !dbg /tmp/s.c:5:3
+; CHECK-NOT:     !dbg
+; CHECK-NEXT:    EMIT vp<[[NOT1:%.+]]> = not ir<%cmp1>, !dbg /tmp/s.c:9:3
 ; CHECK-NEXT:    WIDEN ir<%cmp2> = icmp sge ir<%lsd>, ir<200>
-; CHECK-NEXT:    EMIT vp<[[SEL1:%.+]]> = logical-and vp<[[NOT1]]>, ir<%cmp2>, !dbg /tmp/s.c:5:21
+; CHECK-NOT:     !dbg
+; CHECK-NEXT:    EMIT vp<[[SEL1:%.+]]> = logical-and vp<[[NOT1]]>, ir<%cmp2>, !dbg /tmp/s.c:11:3
 ; CHECK-NEXT:    EMIT vp<[[OR1:%.+]]> = or vp<[[SEL1]]>, ir<%cmp1>
 ; CHECK-NEXT:  Successor(s): pred.sdiv
 ; CHECK-EMPTY:
@@ -365,18 +371,23 @@ define void @debug_loc_vpinstruction(ptr nocapture %asd, ptr nocapture %bsd) !db
 ; CHECK-EMPTY:
 ; CHECK-NEXT:    pred.sdiv.if:
 ; CHECK-NEXT:      REPLICATE ir<%sd1> = sdiv ir<%psd>, ir<%lsd> (S->V)
+; CHECK-NOT:       !dbg
 ; CHECK-NEXT:    Successor(s): pred.sdiv.continue
 ; CHECK-EMPTY:
 ; CHECK-NEXT:    pred.sdiv.continue:
 ; CHECK-NEXT:      PHI-PREDICATED-INSTRUCTION vp<[[PHI:%.+]]> = ir<%sd1>
+; CHECK-NOT:       !dbg
 ; CHECK-NEXT:    No successors
 ; CHECK-NEXT:  }
 ; CHECK-NEXT:  Successor(s): if.then.0
 ; CHECK-EMPTY:
 ; CHECK-NEXT:  if.then.0:
 ; CHECK-NEXT:    BLEND ir<%ysd.0> = ir<%psd> vp<[[PHI]]>/vp<[[OR1]]>
+; CHECK-NOT:     !dbg
 ; CHECK-NEXT:    vp<[[VEC_PTR2:%.+]]> = vector-pointer ir<%isd>
+; CHECK-NOT:     !dbg
 ; CHECK-NEXT:    WIDEN store vp<[[VEC_PTR2]]>, ir<%ysd.0>
+; CHECK-NOT:     !dbg
 ; CHECK-NEXT:    EMIT vp<[[CAN_IV_NEXT]]> = add nuw vp<[[CAN_IV]]>, vp<[[VFxUF]]>
 ; CHECK-NEXT:    EMIT branch-on-count vp<[[CAN_IV_NEXT]]>, vp<[[VTC]]>
 ; CHECK-NEXT:  No successors
@@ -406,23 +417,23 @@ entry:
 
 loop:
   %iv = phi i64 [ 0, %entry ], [ %iv.next, %if.end ]
-  %isd = getelementptr inbounds i32, ptr %asd, i64 %iv
-  %lsd = load i32, ptr %isd, align 4
-  %psd = add nuw nsw i32 %lsd, 23
-  %cmp1 = icmp slt i32 %lsd, 100
-  br i1 %cmp1, label %if.then, label %check, !dbg !7
+  %isd = getelementptr inbounds i32, ptr %src, i64 %iv, !dbg !7
+  %lsd = load i32, ptr %isd, align 4, !dbg !8
+  %psd = add nuw nsw i32 %lsd, 23, !dbg !9
+  %cmp1 = icmp slt i32 %lsd, 100, !dbg !10
+  br i1 %cmp1, label %if.then, label %check, !dbg !11
 
 check:
-  %cmp2 = icmp sge i32 %lsd, 200
-  br i1 %cmp2, label %if.then, label %if.end, !dbg !8
+  %cmp2 = icmp sge i32 %lsd, 200, !dbg !12
+  br i1 %cmp2, label %if.then, label %if.end, !dbg !13
 
 if.then:
-  %sd1 = sdiv i32 %psd, %lsd
+  %sd1 = sdiv i32 %psd, %lsd, !dbg !14
   br label %if.end
 
 if.end:
-  %ysd.0 = phi i32 [ %sd1, %if.then ], [ %psd, %check ]
-  store i32 %ysd.0, ptr %isd, align 4
+  %ysd.0 = phi i32 [ %sd1, %if.then ], [ %psd, %check ], !dbg !16
+  store i32 %ysd.0, ptr %isd, align 4, !dbg !17
   %iv.next = add nuw nsw i64 %iv, 1
   %exitcond = icmp eq i64 %iv.next, 128
   br i1 %exitcond, label %exit, label %loop
@@ -1078,4 +1089,15 @@ attributes #0 = { readonly nounwind "vector-function-abi-variant"="_ZGV_LLVM_M2v
 !5 = distinct !DISubprogram(name: "f", scope: !1, file: !1, line: 4, type: !6, scopeLine: 4, flags: DIFlagPrototyped, spFlags: DISPFlagDefinition | DISPFlagOptimized, unit: !0, retainedNodes: !2)
 !6 = !DISubroutineType(types: !2)
 !7 = !DILocation(line: 5, column: 3, scope: !5)
-!8 = !DILocation(line: 5, column: 21, scope: !5)
+!8 = !DILocation(line: 6, column: 3, scope: !5)
+!9 = !DILocation(line: 7, column: 3, scope: !5)
+!10 = !DILocation(line: 8, column: 3, scope: !5)
+!11 = !DILocation(line: 9, column: 3, scope: !5)
+!12 = !DILocation(line: 10, column: 3, scope: !5)
+!13 = !DILocation(line: 11, column: 3, scope: !5)
+!14 = !DILocation(line: 12, column: 3, scope: !5)
+!15 = !DILocation(line: 13, column: 3, scope: !5)
+!16 = !DILocation(line: 14, column: 3, scope: !5)
+!17 = !DILocation(line: 15, column: 3, scope: !5)
+!18 = !DILocation(line: 16, column: 3, scope: !5)
+!19 = !DILocation(line: 17, column: 3, scope: !5)

polly/docs/ReleaseNotes.rst

@@ -17,3 +17,5 @@ In Polly |version| the following important changes have been incorporated.
 
  * Polly's support for the legacy pass manager has been removed.
 
+ * The infrastructure around ScopPasses has been removed.
+

polly/include/polly/CodeGen/CodeGeneration.h

@@ -10,12 +10,16 @@
 #define POLLY_CODEGENERATION_H
 
 #include "polly/CodeGen/IRBuilder.h"
-#include "polly/ScopPass.h"
-#include "llvm/IR/PassManager.h"
+
+namespace llvm {
+class RegionInfo;
+}
 
 namespace polly {
 class IslAstInfo;
 
+using llvm::BasicBlock;
+
 enum VectorizerChoice {
   VECTORIZER_NONE,
   VECTORIZER_STRIPMINE,
@@ -28,11 +32,6 @@ extern VectorizerChoice PollyVectorizerChoice;
 /// UnreachableInst.
 void markBlockUnreachable(BasicBlock &Block, PollyIRBuilder &Builder);
 
-struct CodeGenerationPass final : PassInfoMixin<CodeGenerationPass> {
-  PreservedAnalyses run(Scop &S, ScopAnalysisManager &SAM,
-                        ScopStandardAnalysisResults &AR, SPMUpdater &U);
-};
-
 extern bool PerfMonitoring;
 
 bool runCodeGeneration(Scop &S, llvm::RegionInfo &RI, IslAstInfo &AI);

polly/include/polly/CodeGen/IslAst.h

@@ -22,12 +22,11 @@
 #define POLLY_ISLAST_H
 
 #include "polly/DependenceInfo.h"
-#include "polly/ScopPass.h"
 #include "llvm/ADT/SmallPtrSet.h"
-#include "llvm/IR/PassManager.h"
 #include "isl/ctx.h"
 
 namespace polly {
+using llvm::raw_ostream;
 using llvm::SmallPtrSet;
 
 class Dependences;
@@ -164,24 +163,6 @@ class IslAstInfo {
   ///}
 };
 
-struct IslAstAnalysis : AnalysisInfoMixin<IslAstAnalysis> {
-  static AnalysisKey Key;
-
-  using Result = IslAstInfo;
-
-  IslAstInfo run(Scop &S, ScopAnalysisManager &SAM,
-                 ScopStandardAnalysisResults &SAR);
-};
-
-struct IslAstPrinterPass final : PassInfoMixin<IslAstPrinterPass> {
-  IslAstPrinterPass(raw_ostream &OS) : OS(OS) {}
-
-  PreservedAnalyses run(Scop &S, ScopAnalysisManager &SAM,
-                        ScopStandardAnalysisResults &, SPMUpdater &U);
-
-  raw_ostream &OS;
-};
-
 std::unique_ptr<IslAstInfo> runIslAstGen(Scop &S,
                                          DependenceAnalysis::Result &DA);
 } // namespace polly

polly/include/polly/CodePreparation.h

@@ -13,19 +13,16 @@
 #ifndef POLLY_CODEPREPARATION_H
 #define POLLY_CODEPREPARATION_H
 
-#include "llvm/IR/PassManager.h"
-
 namespace llvm {
 class DominatorTree;
+class Function;
 class LoopInfo;
 class RegionInfo;
 } // namespace llvm
 
 namespace polly {
-struct CodePreparationPass final : llvm::PassInfoMixin<CodePreparationPass> {
-  llvm::PreservedAnalyses run(llvm::Function &F,
-                              llvm::FunctionAnalysisManager &FAM);
-};
+bool runCodePreparation(llvm::Function &F, llvm::DominatorTree *DT,
+                        llvm::LoopInfo *LI, llvm::RegionInfo *RI);
 } // namespace polly
 
 #endif /* POLLY_CODEPREPARATION_H */