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rampitecrampitec
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[AMDGPU] MC support for gfx1250 scale_offset modifier (#149881)
1 parent 2860431 commit a0b854d

17 files changed

+651
-1
lines changed

‎llvm/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp

Lines changed: 27 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -5324,6 +5324,12 @@ bool AMDGPUAsmParser::validateCoherencyBits(const MCInst &Inst,
53245324
unsigned CPol = Inst.getOperand(CPolPos).getImm();
53255325

53265326
if (!isGFX1250()) {
5327+
if (CPol & CPol::SCAL) {
5328+
SMLoc S = getImmLoc(AMDGPUOperand::ImmTyCPol, Operands);
5329+
StringRef CStr(S.getPointer());
5330+
S = SMLoc::getFromPointer(&CStr.data()[CStr.find("scale_offset")]);
5331+
Error(S, "scale_offset is not supported on this GPU");
5332+
}
53275333
if (CPol & CPol::NV) {
53285334
SMLoc S = getImmLoc(AMDGPUOperand::ImmTyCPol, Operands);
53295335
StringRef CStr(S.getPointer());
@@ -5332,6 +5338,13 @@ bool AMDGPUAsmParser::validateCoherencyBits(const MCInst &Inst,
53325338
}
53335339
}
53345340

5341+
if ((CPol & CPol::SCAL) && !supportsScaleOffset(MII, Inst.getOpcode())) {
5342+
SMLoc S = getImmLoc(AMDGPUOperand::ImmTyCPol, Operands);
5343+
StringRef CStr(S.getPointer());
5344+
S = SMLoc::getFromPointer(&CStr.data()[CStr.find("scale_offset")]);
5345+
Error(S, "scale_offset is not supported for this instruction");
5346+
}
5347+
53355348
if (isGFX12Plus())
53365349
return validateTHAndScopeBits(Inst, Operands, CPol);
53375350

@@ -7003,6 +7016,7 @@ ParseStatus AMDGPUAsmParser::parseCPol(OperandVector &Operands) {
70037016
ParseStatus ResTH = ParseStatus::NoMatch;
70047017
ParseStatus ResScope = ParseStatus::NoMatch;
70057018
ParseStatus ResNV = ParseStatus::NoMatch;
7019+
ParseStatus ResScal = ParseStatus::NoMatch;
70067020

70077021
for (;;) {
70087022
if (ResTH.isNoMatch()) {
@@ -7041,10 +7055,22 @@ ParseStatus AMDGPUAsmParser::parseCPol(OperandVector &Operands) {
70417055
}
70427056
}
70437057

7058+
if (ResScal.isNoMatch()) {
7059+
if (trySkipId("scale_offset")) {
7060+
ResScal = ParseStatus::Success;
7061+
CPolVal |= CPol::SCAL;
7062+
continue;
7063+
} else if (trySkipId("no", "scale_offset")) {
7064+
ResScal = ParseStatus::Success;
7065+
continue;
7066+
}
7067+
}
7068+
70447069
break;
70457070
}
70467071

7047-
if (ResTH.isNoMatch() && ResScope.isNoMatch() && ResNV.isNoMatch())
7072+
if (ResTH.isNoMatch() && ResScope.isNoMatch() && ResNV.isNoMatch() &&
7073+
ResScal.isNoMatch())
70487074
return ParseStatus::NoMatch;
70497075

70507076
Operands.push_back(AMDGPUOperand::CreateImm(this, CPolVal, StringLoc,

‎llvm/lib/Target/AMDGPU/FLATInstructions.td

Lines changed: 2 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -2941,6 +2941,7 @@ multiclass VFLAT_Real_gfx12 <bits<8> op, string name = get_FLAT_ps<NAME>.Mnemoni
29412941
let DecoderNamespace = "GFX12";
29422942

29432943
let Inst{25-24} = {ps.is_flat_global, ps.is_flat_scratch};
2944+
let Inst{48} = cpol{CPolBit.SCAL}; // scale offset
29442945
}
29452946
}
29462947

@@ -3170,6 +3171,7 @@ multiclass VFLAT_Real_gfx1250<bits<8> op,
31703171
let DecoderNamespace = "GFX1250";
31713172

31723173
let Inst{25-24} = {ps.is_flat_global, ps.is_flat_scratch};
3174+
let Inst{48} = cpol{CPolBit.SCAL}; // scale offset
31733175
}
31743176
}
31753177

‎llvm/lib/Target/AMDGPU/GCNSubtarget.h

Lines changed: 3 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -1162,6 +1162,9 @@ class GCNSubtarget final : public AMDGPUGenSubtargetInfo,
11621162

11631163
bool hasLshlAddU64Inst() const { return HasLshlAddU64Inst; }
11641164

1165+
// Scalar and global loads support scale_offset bit.
1166+
bool hasScaleOffset() const { return GFX1250Insts; }
1167+
11651168
bool hasFlatGVSMode() const { return FlatGVSMode; }
11661169

11671170
bool enableSIScheduler() const {

‎llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUInstPrinter.cpp

Lines changed: 3 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -157,6 +157,9 @@ void AMDGPUInstPrinter::printCPol(const MCInst *MI, unsigned OpNo,
157157
const int64_t TH = Imm & CPol::TH;
158158
const int64_t Scope = Imm & CPol::SCOPE;
159159

160+
if (Imm & CPol::SCAL)
161+
O << " scale_offset";
162+
160163
printTH(MI, TH, Scope, O);
161164
printScope(Scope, O);
162165

‎llvm/lib/Target/AMDGPU/SIDefines.h

Lines changed: 2 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -402,6 +402,8 @@ enum CPol {
402402

403403
SWZ = 1 << 6, // Swizzle bit
404404

405+
SCAL = 1 << 11, // Scale offset bit
406+
405407
ALL = TH | SCOPE,
406408

407409
// Helper bits

‎llvm/lib/Target/AMDGPU/SIInstrFormats.td

Lines changed: 1 addition & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -318,6 +318,7 @@ def CPolBit {
318318
int DLC = 2;
319319
int SCC = 4;
320320
int NV = 5;
321+
int SCAL = 11;
321322
}
322323

323324
class VOPDstOperand <RegisterClass rc> : RegisterOperand <rc, "printVOPDst">;

‎llvm/lib/Target/AMDGPU/SIInstrInfo.cpp

Lines changed: 13 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -5482,6 +5482,19 @@ bool SIInstrInfo::verifyInstruction(const MachineInstr &MI,
54825482
}
54835483
}
54845484

5485+
if (const MachineOperand *CPol = getNamedOperand(MI, AMDGPU::OpName::cpol)) {
5486+
if (CPol->getImm() & AMDGPU::CPol::SCAL) {
5487+
if (!ST.hasScaleOffset()) {
5488+
ErrInfo = "Subtarget does not support offset scaling";
5489+
return false;
5490+
}
5491+
if (!AMDGPU::supportsScaleOffset(*this, MI.getOpcode())) {
5492+
ErrInfo = "Instruction does not support offset scaling";
5493+
return false;
5494+
}
5495+
}
5496+
}
5497+
54855498
return true;
54865499
}
54875500

‎llvm/lib/Target/AMDGPU/SMInstructions.td

Lines changed: 1 addition & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -1488,6 +1488,7 @@ class SMEM_Real_Load_gfx12<bits<6> op, string ps, string opName, OffsetMode offs
14881488
let Inst{20} = cpol{CPolBit.NV}; // non-volatile
14891489
let Inst{22-21} = cpol{4-3}; // scope
14901490
let Inst{24-23} = cpol{1-0}; // th - only lower 2 bits are supported
1491+
let Inst{56} = cpol{CPolBit.SCAL}; // scale offset
14911492
}
14921493

14931494
multiclass SM_Real_Loads_gfx12<bits<6> op, string ps = NAME> {

‎llvm/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.cpp

Lines changed: 19 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -3228,6 +3228,25 @@ const GcnBufferFormatInfo *getGcnBufferFormatInfo(uint8_t Format,
32283228
: getGfx9BufferFormatInfo(Format);
32293229
}
32303230

3231+
bool supportsScaleOffset(const MCInstrInfo &MII, unsigned Opcode) {
3232+
uint64_t TSFlags = MII.get(Opcode).TSFlags;
3233+
3234+
if (TSFlags & SIInstrFlags::SMRD)
3235+
return !getSMEMIsBuffer(Opcode);
3236+
if (!(TSFlags & SIInstrFlags::FLAT))
3237+
return false;
3238+
3239+
// Only SV and SVS modes are supported.
3240+
if (TSFlags & SIInstrFlags::FlatScratch)
3241+
return hasNamedOperand(Opcode, OpName::vaddr);
3242+
3243+
// Only GVS mode is supported.
3244+
return hasNamedOperand(Opcode, OpName::vaddr) &&
3245+
hasNamedOperand(Opcode, OpName::saddr);
3246+
3247+
return false;
3248+
}
3249+
32313250
bool hasAny64BitVGPROperands(const MCInstrDesc &OpDesc) {
32323251
for (auto OpName : {OpName::vdst, OpName::src0, OpName::src1, OpName::src2}) {
32333252
int Idx = getNamedOperandIdx(OpDesc.getOpcode(), OpName);

‎llvm/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.h

Lines changed: 3 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -1757,6 +1757,9 @@ bool isIntrinsicSourceOfDivergence(unsigned IntrID);
17571757
/// \returns true if the intrinsic is uniform
17581758
bool isIntrinsicAlwaysUniform(unsigned IntrID);
17591759

1760+
/// \returns true if a memory instruction supports scale_offset modifier.
1761+
bool supportsScaleOffset(const MCInstrInfo &MII, unsigned Opcode);
1762+
17601763
/// \returns lds block size in terms of dwords. \p
17611764
/// This is used to calculate the lds size encoded for PAL metadata 3.0+ which
17621765
/// must be defined in terms of bytes.

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