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nikicnikic
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[DataFlowSanitizer] Generate some test checks (NFC) (#161502)
Generate test checks for some dfsan tests with UTC to make them easier to update. For this purpose I've added a `-dfsan-add-global-name-suffix=0` option to avoid the addition of the `.dfsan` suffix on functions, which allows us to use normal UTC check lines. Otherwise we'd have to use `--include-generated-funcs` instead, which produces less nice results, as the check lines are not interleaved with the original functions anymore.
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12 files changed

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‎llvm/lib/Transforms/Instrumentation/DataFlowSanitizer.cpp‎

Lines changed: 8 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -261,6 +261,11 @@ static cl::opt<bool> ClIgnorePersonalityRoutine(
261261
"list, do not create a wrapper for it."),
262262
cl::Hidden, cl::init(false));
263263

264+
static cl::opt<bool> ClAddGlobalNameSuffix(
265+
"dfsan-add-global-name-suffix",
266+
cl::desc("Whether to add .dfsan suffix to global names"), cl::Hidden,
267+
cl::init(true));
268+
264269
static StringRef getGlobalTypeString(const GlobalValue &G) {
265270
// Types of GlobalVariables are always pointer types.
266271
Type *GType = G.getValueType();
@@ -1256,6 +1261,9 @@ DataFlowSanitizer::WrapperKind DataFlowSanitizer::getWrapperKind(Function *F) {
12561261
}
12571262

12581263
void DataFlowSanitizer::addGlobalNameSuffix(GlobalValue *GV) {
1264+
if (!ClAddGlobalNameSuffix)
1265+
return;
1266+
12591267
std::string GVName = std::string(GV->getName()), Suffix = ".dfsan";
12601268
GV->setName(GVName + Suffix);
12611269

‎llvm/test/Instrumentation/DataFlowSanitizer/arith.ll‎

Lines changed: 54 additions & 41 deletions
Original file line numberDiff line numberDiff line change
@@ -1,73 +1,86 @@
1-
; RUN: opt < %s -passes=dfsan -S | FileCheck %s
1+
; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --version 6
2+
; RUN: opt < %s -passes=dfsan -dfsan-add-global-name-suffix=0 -S | FileCheck %s
23
target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128-n8:16:32:64-S128"
34
target triple = "x86_64-unknown-linux-gnu"
45

56
define i8 @add(i8 %a, i8 %b) {
6-
; CHECK: @add.dfsan
7-
; CHECK-DAG: %[[#ALABEL:]] = load i8, ptr @__dfsan_arg_tls, align [[ALIGN:2]]
8-
; CHECK-DAG: %[[#BLABEL:]] = load i8, ptr inttoptr (i64 add (i64 ptrtoint (ptr @__dfsan_arg_tls to i64), i64 2) to ptr), align [[ALIGN]]
9-
; CHECK: %[[#UNION:]] = or i8 %[[#ALABEL]], %[[#BLABEL]]
10-
; CHECK: %c = add i8 %a, %b
11-
; CHECK: store i8 %[[#UNION]], ptr @__dfsan_retval_tls, align [[ALIGN]]
12-
; CHECK: ret i8 %c
7+
; CHECK-LABEL: define i8 @add(
8+
; CHECK-SAME: i8 [[A:%.*]], i8 [[B:%.*]]) {
9+
; CHECK-NEXT: [[TMP1:%.*]] = load i8, ptr inttoptr (i64 add (i64 ptrtoint (ptr @__dfsan_arg_tls to i64), i64 2) to ptr), align 2
10+
; CHECK-NEXT: [[TMP2:%.*]] = load i8, ptr @__dfsan_arg_tls, align 2
11+
; CHECK-NEXT: [[TMP3:%.*]] = or i8 [[TMP2]], [[TMP1]]
12+
; CHECK-NEXT: [[C:%.*]] = add i8 [[A]], [[B]]
13+
; CHECK-NEXT: store i8 [[TMP3]], ptr @__dfsan_retval_tls, align 2
14+
; CHECK-NEXT: ret i8 [[C]]
15+
;
1316
%c = add i8 %a, %b
1417
ret i8 %c
1518
}
1619

1720
define i8 @sub(i8 %a, i8 %b) {
18-
; CHECK: @sub.dfsan
19-
; CHECK: load{{.*}}__dfsan_arg_tls
20-
; CHECK: load{{.*}}__dfsan_arg_tls
21-
; CHECK: or i8
22-
; CHECK: %c = sub i8 %a, %b
23-
; CHECK: store{{.*}}__dfsan_retval_tls
24-
; CHECK: ret i8 %c
21+
; CHECK-LABEL: define i8 @sub(
22+
; CHECK-SAME: i8 [[A:%.*]], i8 [[B:%.*]]) {
23+
; CHECK-NEXT: [[TMP1:%.*]] = load i8, ptr inttoptr (i64 add (i64 ptrtoint (ptr @__dfsan_arg_tls to i64), i64 2) to ptr), align 2
24+
; CHECK-NEXT: [[TMP2:%.*]] = load i8, ptr @__dfsan_arg_tls, align 2
25+
; CHECK-NEXT: [[TMP3:%.*]] = or i8 [[TMP2]], [[TMP1]]
26+
; CHECK-NEXT: [[C:%.*]] = sub i8 [[A]], [[B]]
27+
; CHECK-NEXT: store i8 [[TMP3]], ptr @__dfsan_retval_tls, align 2
28+
; CHECK-NEXT: ret i8 [[C]]
29+
;
2530
%c = sub i8 %a, %b
2631
ret i8 %c
2732
}
2833

2934
define i8 @mul(i8 %a, i8 %b) {
30-
; CHECK: @mul.dfsan
31-
; CHECK: load{{.*}}__dfsan_arg_tls
32-
; CHECK: load{{.*}}__dfsan_arg_tls
33-
; CHECK: or i8
34-
; CHECK: %c = mul i8 %a, %b
35-
; CHECK: store{{.*}}__dfsan_retval_tls
36-
; CHECK: ret i8 %c
35+
; CHECK-LABEL: define i8 @mul(
36+
; CHECK-SAME: i8 [[A:%.*]], i8 [[B:%.*]]) {
37+
; CHECK-NEXT: [[TMP1:%.*]] = load i8, ptr inttoptr (i64 add (i64 ptrtoint (ptr @__dfsan_arg_tls to i64), i64 2) to ptr), align 2
38+
; CHECK-NEXT: [[TMP2:%.*]] = load i8, ptr @__dfsan_arg_tls, align 2
39+
; CHECK-NEXT: [[TMP3:%.*]] = or i8 [[TMP2]], [[TMP1]]
40+
; CHECK-NEXT: [[C:%.*]] = mul i8 [[A]], [[B]]
41+
; CHECK-NEXT: store i8 [[TMP3]], ptr @__dfsan_retval_tls, align 2
42+
; CHECK-NEXT: ret i8 [[C]]
43+
;
3744
%c = mul i8 %a, %b
3845
ret i8 %c
3946
}
4047

4148
define i8 @sdiv(i8 %a, i8 %b) {
42-
; CHECK: @sdiv.dfsan
43-
; CHECK: load{{.*}}__dfsan_arg_tls
44-
; CHECK: load{{.*}}__dfsan_arg_tls
45-
; CHECK: or i8
46-
; CHECK: %c = sdiv i8 %a, %b
47-
; CHECK: store{{.*}}__dfsan_retval_tls
48-
; CHECK: ret i8 %c
49+
; CHECK-LABEL: define i8 @sdiv(
50+
; CHECK-SAME: i8 [[A:%.*]], i8 [[B:%.*]]) {
51+
; CHECK-NEXT: [[TMP1:%.*]] = load i8, ptr inttoptr (i64 add (i64 ptrtoint (ptr @__dfsan_arg_tls to i64), i64 2) to ptr), align 2
52+
; CHECK-NEXT: [[TMP2:%.*]] = load i8, ptr @__dfsan_arg_tls, align 2
53+
; CHECK-NEXT: [[TMP3:%.*]] = or i8 [[TMP2]], [[TMP1]]
54+
; CHECK-NEXT: [[C:%.*]] = sdiv i8 [[A]], [[B]]
55+
; CHECK-NEXT: store i8 [[TMP3]], ptr @__dfsan_retval_tls, align 2
56+
; CHECK-NEXT: ret i8 [[C]]
57+
;
4958
%c = sdiv i8 %a, %b
5059
ret i8 %c
5160
}
5261

5362
define i8 @udiv(i8 %a, i8 %b) {
54-
; CHECK: @udiv.dfsan
55-
; CHECK: load{{.*}}__dfsan_arg_tls
56-
; CHECK: load{{.*}}__dfsan_arg_tls
57-
; CHECK: or i8
58-
; CHECK: %c = udiv i8 %a, %b
59-
; CHECK: store{{.*}}__dfsan_retval_tls
60-
; CHECK: ret i8 %c
63+
; CHECK-LABEL: define i8 @udiv(
64+
; CHECK-SAME: i8 [[A:%.*]], i8 [[B:%.*]]) {
65+
; CHECK-NEXT: [[TMP1:%.*]] = load i8, ptr inttoptr (i64 add (i64 ptrtoint (ptr @__dfsan_arg_tls to i64), i64 2) to ptr), align 2
66+
; CHECK-NEXT: [[TMP2:%.*]] = load i8, ptr @__dfsan_arg_tls, align 2
67+
; CHECK-NEXT: [[TMP3:%.*]] = or i8 [[TMP2]], [[TMP1]]
68+
; CHECK-NEXT: [[C:%.*]] = udiv i8 [[A]], [[B]]
69+
; CHECK-NEXT: store i8 [[TMP3]], ptr @__dfsan_retval_tls, align 2
70+
; CHECK-NEXT: ret i8 [[C]]
71+
;
6172
%c = udiv i8 %a, %b
6273
ret i8 %c
6374
}
6475

6576
define double @fneg(double %a) {
66-
; CHECK: @fneg.dfsan
67-
; CHECK: load{{.*}}__dfsan_arg_tls
68-
; CHECK: %c = fneg double %a
69-
; CHECK: store{{.*}}__dfsan_retval_tls
70-
; CHECK: ret double %c
77+
; CHECK-LABEL: define double @fneg(
78+
; CHECK-SAME: double [[A:%.*]]) {
79+
; CHECK-NEXT: [[TMP1:%.*]] = load i8, ptr @__dfsan_arg_tls, align 2
80+
; CHECK-NEXT: [[C:%.*]] = fneg double [[A]]
81+
; CHECK-NEXT: store i8 [[TMP1]], ptr @__dfsan_retval_tls, align 2
82+
; CHECK-NEXT: ret double [[C]]
83+
;
7184
%c = fneg double %a
7285
ret double %c
7386
}

‎llvm/test/Instrumentation/DataFlowSanitizer/dont_combine_offset_labels_on_gep.ll‎

Lines changed: 19 additions & 12 deletions
Original file line numberDiff line numberDiff line change
@@ -1,19 +1,26 @@
1-
; RUN: opt < %s -passes=dfsan -dfsan-combine-offset-labels-on-gep=false -S | FileCheck %s
2-
; RUN: opt < %s -passes=dfsan -dfsan-combine-offset-labels-on-gep=false -dfsan-track-origins=1 -S | FileCheck %s --check-prefixes=CHECK,CHECK_ORIGIN
1+
; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --version 6
2+
; RUN: opt < %s -passes=dfsan -dfsan-combine-offset-labels-on-gep=false -dfsan-add-global-name-suffix=0 -S | FileCheck %s
3+
; RUN: opt < %s -passes=dfsan -dfsan-combine-offset-labels-on-gep=false -dfsan-track-origins=1 -dfsan-add-global-name-suffix=0 -S | FileCheck %s --check-prefix=CHECK_ORIGIN
34
target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128-n8:16:32:64-S128"
45
target triple = "x86_64-unknown-linux-gnu"
56

6-
; CHECK: @__dfsan_arg_tls = external thread_local(initialexec) global [[TLS_ARR:\[100 x i64\]]]
7-
; CHECK: @__dfsan_retval_tls = external thread_local(initialexec) global [[TLS_ARR]]
87
define ptr @gepop(ptr %p, i32 %a, i32 %b, i32 %c) {
9-
; CHECK: @gepop.dfsan
10-
; CHECK_ORIGIN: %[[#PO:]] = load i32, ptr @__dfsan_arg_origin_tls, align [[ALIGN_O:4]]
11-
; CHECK: %[[#PS:]] = load i8, ptr @__dfsan_arg_tls, align [[ALIGN_S:2]]
12-
; CHECK: %e = getelementptr [10 x [20 x i32]], ptr %p, i32 %a, i32 %b, i32 %c
13-
; CHECK: store i8 %[[#PS]], ptr @__dfsan_retval_tls, align [[ALIGN_S]]
14-
; CHECK_ORIGIN: store i32 %[[#PO]], ptr @__dfsan_retval_origin_tls, align [[ALIGN_O]]
15-
8+
; CHECK-LABEL: define ptr @gepop(
9+
; CHECK-SAME: ptr [[P:%.*]], i32 [[A:%.*]], i32 [[B:%.*]], i32 [[C:%.*]]) {
10+
; CHECK-NEXT: [[TMP1:%.*]] = load i8, ptr @__dfsan_arg_tls, align 2
11+
; CHECK-NEXT: [[E:%.*]] = getelementptr [10 x [20 x i32]], ptr [[P]], i32 [[A]], i32 [[B]], i32 [[C]]
12+
; CHECK-NEXT: store i8 [[TMP1]], ptr @__dfsan_retval_tls, align 2
13+
; CHECK-NEXT: ret ptr [[E]]
14+
;
15+
; CHECK_ORIGIN-LABEL: define ptr @gepop(
16+
; CHECK_ORIGIN-SAME: ptr [[P:%.*]], i32 [[A:%.*]], i32 [[B:%.*]], i32 [[C:%.*]]) {
17+
; CHECK_ORIGIN-NEXT: [[TMP1:%.*]] = load i32, ptr @__dfsan_arg_origin_tls, align 4
18+
; CHECK_ORIGIN-NEXT: [[TMP2:%.*]] = load i8, ptr @__dfsan_arg_tls, align 2
19+
; CHECK_ORIGIN-NEXT: [[E:%.*]] = getelementptr [10 x [20 x i32]], ptr [[P]], i32 [[A]], i32 [[B]], i32 [[C]]
20+
; CHECK_ORIGIN-NEXT: store i8 [[TMP2]], ptr @__dfsan_retval_tls, align 2
21+
; CHECK_ORIGIN-NEXT: store i32 [[TMP1]], ptr @__dfsan_retval_origin_tls, align 4
22+
; CHECK_ORIGIN-NEXT: ret ptr [[E]]
23+
;
1624
%e = getelementptr [10 x [20 x i32]], ptr %p, i32 %a, i32 %b, i32 %c
1725
ret ptr %e
1826
}
19-

‎llvm/test/Instrumentation/DataFlowSanitizer/origin_cached_shadows.ll‎

Lines changed: 127 additions & 37 deletions
Original file line numberDiff line numberDiff line change
@@ -1,4 +1,5 @@
1-
; RUN: opt < %s -passes=dfsan -dfsan-track-origins=1 -S | FileCheck %s
1+
; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --version 6
2+
; RUN: opt < %s -passes=dfsan -dfsan-track-origins=1 -dfsan-add-global-name-suffix=0 -S | FileCheck %s
23
;
34
; %i13 and %i15 have the same key in shadow cache. They should not reuse the same
45
; shadow because their blocks do not dominate each other. Origin tracking
@@ -7,43 +8,129 @@
78
target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128-n8:16:32:64-S128"
89
target triple = "x86_64-unknown-linux-gnu"
910

10-
; CHECK: @__dfsan_arg_tls = external thread_local(initialexec) global [[TLS_ARR:\[100 x i64\]]]
1111
define void @cached_shadows(double %arg) {
12-
; CHECK: @cached_shadows.dfsan
13-
; CHECK: [[AO:%.*]] = load i32, ptr @__dfsan_arg_origin_tls, align
14-
; CHECK: [[AS:%.*]] = load i8, ptr @__dfsan_arg_tls, align [[ALIGN:2]]
15-
; CHECK: [[L1:.+]]:
16-
; CHECK: {{.*}} = phi i8
17-
; CHECK: {{.*}} = phi i32
18-
; CHECK: {{.*}} = phi double [ 3.000000e+00
19-
; CHECK: [[S_L1:%.*]] = phi i8 [ 0, %[[L0:.*]] ], [ [[S_L7:%.*]], %[[L7:.*]] ]
20-
; CHECK: [[O_L1:%.*]] = phi i32 [ 0, %[[L0]] ], [ [[O_L7:%.*]], %[[L7]] ]
21-
; CHECK: [[V_L1:%.*]] = phi double [ 4.000000e+00, %[[L0]] ], [ [[V_L7:%.*]], %[[L7]] ]
22-
; CHECK: br i1 {{%.+}}, label %[[L2:.*]], label %[[L4:.*]]
23-
; CHECK: [[L2]]:
24-
; CHECK: br i1 {{%.+}}, label %[[L3:.+]], label %[[L7]]
25-
; CHECK: [[L3]]:
26-
; CHECK: [[S_L3:%.*]] = or i8
27-
; CHECK: [[AS_NE_L3:%.*]] = icmp ne i8 [[AS]], 0
28-
; CHECK: [[O_L3:%.*]] = select i1 [[AS_NE_L3]], i32 %{{[0-9]+}}, i32 [[O_L1]]
29-
; CHECK: [[V_L3:%.*]] = fsub double [[V_L1]], %{{.+}}
30-
; CHECK: br label %[[L7]]
31-
; CHECK: [[L4]]:
32-
; CHECK: br i1 %_dfscmp, label %[[L5:.+]], label %[[L6:.+]],
33-
; CHECK: [[L5]]:
34-
; CHECK: br label %[[L6]]
35-
; CHECK: [[L6]]:
36-
; CHECK: [[S_L6:%.*]] = or i8
37-
; CHECK: [[AS_NE_L6:%.*]] = icmp ne i8 [[AS]], 0
38-
; CHECK: [[O_L6:%.*]] = select i1 [[AS_NE_L6]], i32 [[AO]], i32 [[O_L1]]
39-
; CHECK: [[V_L6:%.*]] = fadd double [[V_L1]], %{{.+}}
40-
; CHECK: br label %[[L7]]
41-
; CHECK: [[L7]]:
42-
; CHECK: [[S_L7]] = phi i8 [ [[S_L3]], %[[L3]] ], [ [[S_L1]], %[[L2]] ], [ [[S_L6]], %[[L6]] ]
43-
; CHECK: [[O_L7]] = phi i32 [ [[O_L3]], %[[L3]] ], [ [[O_L1]], %[[L2]] ], [ [[O_L6]], %[[L6]] ]
44-
; CHECK: [[V_L7]] = phi double [ [[V_L3]], %[[L3]] ], [ [[V_L1]], %[[L2]] ], [ [[V_L6]], %[[L6]] ]
45-
; CHECK: br i1 %{{.+}}, label %[[L1]], label %[[L8:.+]]
46-
; CHECK: [[L8]]:
12+
; CHECK-LABEL: define void @cached_shadows(
13+
; CHECK-SAME: double [[ARG:%.*]]) {
14+
; CHECK-NEXT: [[BB:.*]]:
15+
; CHECK-NEXT: [[TMP0:%.*]] = load i32, ptr @__dfsan_arg_origin_tls, align 4
16+
; CHECK-NEXT: [[TMP1:%.*]] = load i8, ptr @__dfsan_arg_tls, align 2
17+
; CHECK-NEXT: [[I:%.*]] = alloca double, align 8
18+
; CHECK-NEXT: [[I1:%.*]] = alloca double, align 8
19+
; CHECK-NEXT: [[I2:%.*]] = bitcast ptr [[I]] to ptr
20+
; CHECK-NEXT: [[TMP2:%.*]] = ptrtoint ptr [[I]] to i64
21+
; CHECK-NEXT: [[TMP3:%.*]] = xor i64 [[TMP2]], 87960930222080
22+
; CHECK-NEXT: [[TMP4:%.*]] = inttoptr i64 [[TMP3]] to ptr
23+
; CHECK-NEXT: store i64 0, ptr [[TMP4]], align 1
24+
; CHECK-NEXT: store volatile double 1.000000e+00, ptr [[I]], align 8
25+
; CHECK-NEXT: [[I3:%.*]] = bitcast ptr [[I1]] to ptr
26+
; CHECK-NEXT: [[TMP5:%.*]] = ptrtoint ptr [[I1]] to i64
27+
; CHECK-NEXT: [[TMP6:%.*]] = xor i64 [[TMP5]], 87960930222080
28+
; CHECK-NEXT: [[TMP7:%.*]] = inttoptr i64 [[TMP6]] to ptr
29+
; CHECK-NEXT: store i64 0, ptr [[TMP7]], align 1
30+
; CHECK-NEXT: store volatile double 2.000000e+00, ptr [[I1]], align 8
31+
; CHECK-NEXT: br label %[[BB4:.*]]
32+
; CHECK: [[BB4]]:
33+
; CHECK-NEXT: [[TMP8:%.*]] = phi i8 [ 0, %[[BB]] ], [ [[TMP76:%.*]], %[[BB16:.*]] ]
34+
; CHECK-NEXT: [[TMP9:%.*]] = phi i32 [ 0, %[[BB]] ], [ [[TMP77:%.*]], %[[BB16]] ]
35+
; CHECK-NEXT: [[I5:%.*]] = phi double [ 3.000000e+00, %[[BB]] ], [ [[I17:%.*]], %[[BB16]] ]
36+
; CHECK-NEXT: [[TMP10:%.*]] = phi i8 [ 0, %[[BB]] ], [ [[TMP78:%.*]], %[[BB16]] ]
37+
; CHECK-NEXT: [[TMP11:%.*]] = phi i32 [ 0, %[[BB]] ], [ [[TMP79:%.*]], %[[BB16]] ]
38+
; CHECK-NEXT: [[I6:%.*]] = phi double [ 4.000000e+00, %[[BB]] ], [ [[I18:%.*]], %[[BB16]] ]
39+
; CHECK-NEXT: [[TMP12:%.*]] = ptrtoint ptr [[I1]] to i64
40+
; CHECK-NEXT: [[TMP13:%.*]] = xor i64 [[TMP12]], 87960930222080
41+
; CHECK-NEXT: [[TMP14:%.*]] = inttoptr i64 [[TMP13]] to ptr
42+
; CHECK-NEXT: [[TMP15:%.*]] = add i64 [[TMP13]], 17592186044416
43+
; CHECK-NEXT: [[TMP16:%.*]] = inttoptr i64 [[TMP15]] to ptr
44+
; CHECK-NEXT: [[TMP17:%.*]] = load i32, ptr [[TMP16]], align 8
45+
; CHECK-NEXT: [[TMP18:%.*]] = load i64, ptr [[TMP14]], align 1
46+
; CHECK-NEXT: [[TMP19:%.*]] = shl i64 [[TMP18]], 32
47+
; CHECK-NEXT: [[TMP20:%.*]] = getelementptr i32, ptr [[TMP16]], i64 1
48+
; CHECK-NEXT: [[TMP21:%.*]] = load i32, ptr [[TMP20]], align 8
49+
; CHECK-NEXT: [[TMP22:%.*]] = lshr i64 [[TMP18]], 32
50+
; CHECK-NEXT: [[TMP23:%.*]] = or i64 [[TMP18]], [[TMP22]]
51+
; CHECK-NEXT: [[TMP24:%.*]] = lshr i64 [[TMP23]], 16
52+
; CHECK-NEXT: [[TMP25:%.*]] = or i64 [[TMP23]], [[TMP24]]
53+
; CHECK-NEXT: [[TMP26:%.*]] = lshr i64 [[TMP25]], 8
54+
; CHECK-NEXT: [[TMP27:%.*]] = or i64 [[TMP25]], [[TMP26]]
55+
; CHECK-NEXT: [[TMP28:%.*]] = trunc i64 [[TMP27]] to i8
56+
; CHECK-NEXT: [[TMP29:%.*]] = icmp ne i64 [[TMP19]], 0
57+
; CHECK-NEXT: [[TMP30:%.*]] = select i1 [[TMP29]], i32 [[TMP17]], i32 [[TMP21]]
58+
; CHECK-NEXT: [[I7:%.*]] = load volatile double, ptr [[I1]], align 8
59+
; CHECK-NEXT: [[I8:%.*]] = fcmp une double [[I7]], 0.000000e+00
60+
; CHECK-NEXT: [[TMP31:%.*]] = ptrtoint ptr [[I1]] to i64
61+
; CHECK-NEXT: [[TMP32:%.*]] = xor i64 [[TMP31]], 87960930222080
62+
; CHECK-NEXT: [[TMP33:%.*]] = inttoptr i64 [[TMP32]] to ptr
63+
; CHECK-NEXT: [[TMP34:%.*]] = add i64 [[TMP32]], 17592186044416
64+
; CHECK-NEXT: [[TMP35:%.*]] = inttoptr i64 [[TMP34]] to ptr
65+
; CHECK-NEXT: [[TMP36:%.*]] = load i32, ptr [[TMP35]], align 8
66+
; CHECK-NEXT: [[TMP37:%.*]] = load i64, ptr [[TMP33]], align 1
67+
; CHECK-NEXT: [[TMP38:%.*]] = shl i64 [[TMP37]], 32
68+
; CHECK-NEXT: [[TMP39:%.*]] = getelementptr i32, ptr [[TMP35]], i64 1
69+
; CHECK-NEXT: [[TMP40:%.*]] = load i32, ptr [[TMP39]], align 8
70+
; CHECK-NEXT: [[TMP41:%.*]] = lshr i64 [[TMP37]], 32
71+
; CHECK-NEXT: [[TMP42:%.*]] = or i64 [[TMP37]], [[TMP41]]
72+
; CHECK-NEXT: [[TMP43:%.*]] = lshr i64 [[TMP42]], 16
73+
; CHECK-NEXT: [[TMP44:%.*]] = or i64 [[TMP42]], [[TMP43]]
74+
; CHECK-NEXT: [[TMP45:%.*]] = lshr i64 [[TMP44]], 8
75+
; CHECK-NEXT: [[TMP46:%.*]] = or i64 [[TMP44]], [[TMP45]]
76+
; CHECK-NEXT: [[TMP47:%.*]] = trunc i64 [[TMP46]] to i8
77+
; CHECK-NEXT: [[TMP48:%.*]] = icmp ne i64 [[TMP38]], 0
78+
; CHECK-NEXT: [[TMP49:%.*]] = select i1 [[TMP48]], i32 [[TMP36]], i32 [[TMP40]]
79+
; CHECK-NEXT: [[I9:%.*]] = load volatile double, ptr [[I1]], align 8
80+
; CHECK-NEXT: br i1 [[I8]], label %[[BB10:.*]], label %[[BB14:.*]]
81+
; CHECK: [[BB10]]:
82+
; CHECK-NEXT: [[I11:%.*]] = fcmp une double [[I9]], 0.000000e+00
83+
; CHECK-NEXT: br i1 [[I11]], label %[[BB12:.*]], label %[[BB16]]
84+
; CHECK: [[BB12]]:
85+
; CHECK-NEXT: [[TMP50:%.*]] = or i8 [[TMP10]], [[TMP1]]
86+
; CHECK-NEXT: [[TMP51:%.*]] = icmp ne i8 [[TMP1]], 0
87+
; CHECK-NEXT: [[TMP52:%.*]] = select i1 [[TMP51]], i32 [[TMP0]], i32 [[TMP11]]
88+
; CHECK-NEXT: [[I13:%.*]] = fsub double [[I6]], [[ARG]]
89+
; CHECK-NEXT: br label %[[BB16]]
90+
; CHECK: [[BB14]]:
91+
; CHECK-NEXT: [[TMP53:%.*]] = ptrtoint ptr [[I]] to i64
92+
; CHECK-NEXT: [[TMP54:%.*]] = xor i64 [[TMP53]], 87960930222080
93+
; CHECK-NEXT: [[TMP55:%.*]] = inttoptr i64 [[TMP54]] to ptr
94+
; CHECK-NEXT: [[TMP56:%.*]] = add i64 [[TMP54]], 17592186044416
95+
; CHECK-NEXT: [[TMP57:%.*]] = inttoptr i64 [[TMP56]] to ptr
96+
; CHECK-NEXT: [[TMP58:%.*]] = insertelement <8 x i8> poison, i8 [[TMP47]], i32 0
97+
; CHECK-NEXT: [[TMP59:%.*]] = insertelement <8 x i8> [[TMP58]], i8 [[TMP47]], i32 1
98+
; CHECK-NEXT: [[TMP60:%.*]] = insertelement <8 x i8> [[TMP59]], i8 [[TMP47]], i32 2
99+
; CHECK-NEXT: [[TMP61:%.*]] = insertelement <8 x i8> [[TMP60]], i8 [[TMP47]], i32 3
100+
; CHECK-NEXT: [[TMP62:%.*]] = insertelement <8 x i8> [[TMP61]], i8 [[TMP47]], i32 4
101+
; CHECK-NEXT: [[TMP63:%.*]] = insertelement <8 x i8> [[TMP62]], i8 [[TMP47]], i32 5
102+
; CHECK-NEXT: [[TMP64:%.*]] = insertelement <8 x i8> [[TMP63]], i8 [[TMP47]], i32 6
103+
; CHECK-NEXT: [[TMP65:%.*]] = insertelement <8 x i8> [[TMP64]], i8 [[TMP47]], i32 7
104+
; CHECK-NEXT: [[TMP66:%.*]] = getelementptr <8 x i8>, ptr [[TMP55]], i32 0
105+
; CHECK-NEXT: store <8 x i8> [[TMP65]], ptr [[TMP66]], align 1
106+
; CHECK-NEXT: [[_DFSCMP:%.*]] = icmp ne i8 [[TMP47]], 0
107+
; CHECK-NEXT: br i1 [[_DFSCMP]], label %[[BB67:.*]], label %[[BB72:.*]], !prof [[PROF1:![0-9]+]]
108+
; CHECK: [[BB67]]:
109+
; CHECK-NEXT: [[TMP68:%.*]] = call i32 @__dfsan_chain_origin(i32 [[TMP49]])
110+
; CHECK-NEXT: [[TMP69:%.*]] = zext i32 [[TMP68]] to i64
111+
; CHECK-NEXT: [[TMP70:%.*]] = shl i64 [[TMP69]], 32
112+
; CHECK-NEXT: [[TMP71:%.*]] = or i64 [[TMP69]], [[TMP70]]
113+
; CHECK-NEXT: store i64 [[TMP71]], ptr [[TMP57]], align 8
114+
; CHECK-NEXT: br label %[[BB72]]
115+
; CHECK: [[BB72]]:
116+
; CHECK-NEXT: store volatile double [[I9]], ptr [[I]], align 8
117+
; CHECK-NEXT: [[TMP73:%.*]] = or i8 [[TMP10]], [[TMP1]]
118+
; CHECK-NEXT: [[TMP74:%.*]] = icmp ne i8 [[TMP1]], 0
119+
; CHECK-NEXT: [[TMP75:%.*]] = select i1 [[TMP74]], i32 [[TMP0]], i32 [[TMP11]]
120+
; CHECK-NEXT: [[I15:%.*]] = fadd double [[I6]], [[ARG]]
121+
; CHECK-NEXT: br label %[[BB16]]
122+
; CHECK: [[BB16]]:
123+
; CHECK-NEXT: [[TMP76]] = phi i8 [ [[TMP10]], %[[BB12]] ], [ [[TMP8]], %[[BB10]] ], [ [[TMP10]], %[[BB72]] ]
124+
; CHECK-NEXT: [[TMP77]] = phi i32 [ [[TMP11]], %[[BB12]] ], [ [[TMP9]], %[[BB10]] ], [ [[TMP11]], %[[BB72]] ]
125+
; CHECK-NEXT: [[I17]] = phi double [ [[I6]], %[[BB12]] ], [ [[I5]], %[[BB10]] ], [ [[I6]], %[[BB72]] ]
126+
; CHECK-NEXT: [[TMP78]] = phi i8 [ [[TMP50]], %[[BB12]] ], [ [[TMP10]], %[[BB10]] ], [ [[TMP73]], %[[BB72]] ]
127+
; CHECK-NEXT: [[TMP79]] = phi i32 [ [[TMP52]], %[[BB12]] ], [ [[TMP11]], %[[BB10]] ], [ [[TMP75]], %[[BB72]] ]
128+
; CHECK-NEXT: [[I18]] = phi double [ [[I13]], %[[BB12]] ], [ [[I6]], %[[BB10]] ], [ [[I15]], %[[BB72]] ]
129+
; CHECK-NEXT: [[I19:%.*]] = fcmp olt double [[I17]], 9.900000e+01
130+
; CHECK-NEXT: br i1 [[I19]], label %[[BB4]], label %[[BB20:.*]]
131+
; CHECK: [[BB20]]:
132+
; CHECK-NEXT: ret void
133+
;
47134
bb:
48135
%i = alloca double, align 8
49136
%i1 = alloca double, align 8
@@ -83,3 +170,6 @@ bb16: ; preds = %bb14, %bb12, %bb10
83170
bb20: ; preds = %bb16
84171
ret void
85172
}
173+
;.
174+
; CHECK: [[PROF1]] = !{!"branch_weights", i32 1, i32 1048575}
175+
;.

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