fixup! getScalarSizeInBits.

topperc · topperc · commit a0fb8db95f57 · 2024-11-06T16:51:51.000-08:00
diff --git a/llvm/lib/Target/RISCV/GISel/RISCVInstructionSelector.cpp b/llvm/lib/Target/RISCV/GISel/RISCVInstructionSelector.cpp
@@ -261,7 +261,7 @@ RISCVInstructionSelector::selectZExtBits(MachineOperand &Root,
     return {{[=](MachineInstrBuilder &MIB) { MIB.addReg(RegX); }}};
   }
 
-  unsigned Size = MRI->getType(RootReg).getSizeInBits();
+  unsigned Size = MRI->getType(RootReg).getScalarSizeInBits();
   if (KB->maskedValueIsZero(RootReg, APInt::getBitsSetFrom(Size, Bits)))
     return {{[=](MachineInstrBuilder &MIB) { MIB.add(Root); }}};
 

Original file line number	Diff line number	Diff line change
`@@ -261,7 +261,7 @@ RISCVInstructionSelector::selectZExtBits(MachineOperand &Root,`
`261`	`261`	`return {{[=](MachineInstrBuilder &MIB) { MIB.addReg(RegX); }}};`
`262`	`262`	`}`
`263`	`263`
`264`		`- unsigned Size = MRI->getType(RootReg).getSizeInBits();`
	`264`	`+ unsigned Size = MRI->getType(RootReg).getScalarSizeInBits();`
`265`	`265`	`if (KB->maskedValueIsZero(RootReg, APInt::getBitsSetFrom(Size, Bits)))`
`266`	`266`	`return {{[=](MachineInstrBuilder &MIB) { MIB.add(Root); }}};`
`267`	`267`