Skip to content

Commit a160e51

Browse files
s-barannikovs-barannikov
authored
[AArch64] Fix SDNode type mismatches between *.td files and ISel (#116523)
* `MRS`, `PTEST` and FP comparisons were missing "flags" result, and were sometimes created with invalid types (f32, Glue, Other). * `REV16`, `REV32`, `REV64`, and `CMGEz` were sometimes created with an extra operand. * `TLSDESC_CALLSEQ` had `SDNPInGlue` property, but the node was never created with a glue operand.
1 parent 05bcf83 commit a160e51

File tree

5 files changed

+30
-27
lines changed

5 files changed

+30
-27
lines changed

‎llvm/lib/Target/AArch64/AArch64ISelLowering.cpp‎

Lines changed: 9 additions & 11 deletions
Original file line numberDiff line numberDiff line change
@@ -3547,11 +3547,10 @@ static SDValue emitStrictFPComparison(SDValue LHS, SDValue RHS, const SDLoc &dl,
35473547
RHS = DAG.getNode(ISD::STRICT_FP_EXTEND, dl, {MVT::f32, MVT::Other},
35483548
{LHS.getValue(1), RHS});
35493549
Chain = RHS.getValue(1);
3550-
VT = MVT::f32;
35513550
}
35523551
unsigned Opcode =
35533552
IsSignaling ? AArch64ISD::STRICT_FCMPE : AArch64ISD::STRICT_FCMP;
3554-
return DAG.getNode(Opcode, dl, {VT, MVT::Other}, {Chain, LHS, RHS});
3553+
return DAG.getNode(Opcode, dl, {MVT::i32, MVT::Other}, {Chain, LHS, RHS});
35553554
}
35563555

35573556
static SDValue emitComparison(SDValue LHS, SDValue RHS, ISD::CondCode CC,
@@ -3564,9 +3563,8 @@ static SDValue emitComparison(SDValue LHS, SDValue RHS, ISD::CondCode CC,
35643563
if ((VT == MVT::f16 && !FullFP16) || VT == MVT::bf16) {
35653564
LHS = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f32, LHS);
35663565
RHS = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f32, RHS);
3567-
VT = MVT::f32;
35683566
}
3569-
return DAG.getNode(AArch64ISD::FCMP, dl, VT, LHS, RHS);
3567+
return DAG.getNode(AArch64ISD::FCMP, dl, MVT::i32, LHS, RHS);
35703568
}
35713569

35723570
// The CMP instruction is just an alias for SUBS, and representing it as
@@ -13660,11 +13658,11 @@ SDValue AArch64TargetLowering::LowerVECTOR_SHUFFLE(SDValue Op,
1366013658
unsigned NumElts = VT.getVectorNumElements();
1366113659
unsigned EltSize = VT.getScalarSizeInBits();
1366213660
if (isREVMask(ShuffleMask, EltSize, NumElts, 64))
13663-
return DAG.getNode(AArch64ISD::REV64, dl, V1.getValueType(), V1, V2);
13661+
return DAG.getNode(AArch64ISD::REV64, dl, V1.getValueType(), V1);
1366413662
if (isREVMask(ShuffleMask, EltSize, NumElts, 32))
13665-
return DAG.getNode(AArch64ISD::REV32, dl, V1.getValueType(), V1, V2);
13663+
return DAG.getNode(AArch64ISD::REV32, dl, V1.getValueType(), V1);
1366613664
if (isREVMask(ShuffleMask, EltSize, NumElts, 16))
13667-
return DAG.getNode(AArch64ISD::REV16, dl, V1.getValueType(), V1, V2);
13665+
return DAG.getNode(AArch64ISD::REV16, dl, V1.getValueType(), V1);
1366813666

1366913667
if (((NumElts == 8 && EltSize == 16) || (NumElts == 16 && EltSize == 8)) &&
1367013668
ShuffleVectorInst::isReverseMask(ShuffleMask, ShuffleMask.size())) {
@@ -15681,7 +15679,7 @@ static SDValue EmitVectorComparison(SDValue LHS, SDValue RHS,
1568115679
if (IsZero)
1568215680
return DAG.getNode(AArch64ISD::CMGTz, dl, VT, LHS);
1568315681
if (IsMinusOne)
15684-
return DAG.getNode(AArch64ISD::CMGEz, dl, VT, LHS, RHS);
15682+
return DAG.getNode(AArch64ISD::CMGEz, dl, VT, LHS);
1568515683
return DAG.getNode(AArch64ISD::CMGT, dl, VT, LHS, RHS);
1568615684
case AArch64CC::LE:
1568715685
if (IsZero)
@@ -21568,7 +21566,7 @@ static SDValue getPTest(SelectionDAG &DAG, EVT VT, SDValue Pg, SDValue Op,
2156821566
// Set condition code (CC) flags.
2156921567
SDValue Test = DAG.getNode(
2157021568
Cond == AArch64CC::ANY_ACTIVE ? AArch64ISD::PTEST_ANY : AArch64ISD::PTEST,
21571-
DL, MVT::Other, Pg, Op);
21569+
DL, MVT::i32, Pg, Op);
2157221570

2157321571
// Convert CC to integer based on requested condition.
2157421572
// NOTE: Cond is inverted to promote CSEL's removal when it feeds a compare.
@@ -26374,8 +26372,8 @@ SDValue AArch64TargetLowering::PerformDAGCombine(SDNode *N,
2637426372
: AArch64SysReg::RNDRRS);
2637526373
SDLoc DL(N);
2637626374
SDValue A = DAG.getNode(
26377-
AArch64ISD::MRS, DL, DAG.getVTList(MVT::i64, MVT::Glue, MVT::Other),
26378-
N->getOperand(0), DAG.getConstant(Register, DL, MVT::i64));
26375+
AArch64ISD::MRS, DL, DAG.getVTList(MVT::i64, MVT::i32, MVT::Other),
26376+
N->getOperand(0), DAG.getConstant(Register, DL, MVT::i32));
2637926377
SDValue B = DAG.getNode(
2638026378
AArch64ISD::CSINC, DL, MVT::i32, DAG.getConstant(0, DL, MVT::i32),
2638126379
DAG.getConstant(0, DL, MVT::i32),

‎llvm/lib/Target/AArch64/AArch64InstrFormats.td‎

Lines changed: 6 additions & 6 deletions
Original file line numberDiff line numberDiff line change
@@ -5911,34 +5911,34 @@ multiclass FPComparison<bit signalAllNans, string asm,
59115911
SDPatternOperator OpNode = null_frag> {
59125912
let Defs = [NZCV] in {
59135913
def Hrr : BaseTwoOperandFPComparison<signalAllNans, FPR16, asm,
5914-
[(OpNode (f16 FPR16:$Rn), (f16 FPR16:$Rm))]> {
5914+
[(set NZCV, (OpNode (f16 FPR16:$Rn), (f16 FPR16:$Rm)))]> {
59155915
let Inst{23-22} = 0b11;
59165916
let Predicates = [HasFullFP16];
59175917
}
59185918

59195919
def Hri : BaseOneOperandFPComparison<signalAllNans, FPR16, asm,
5920-
[(OpNode (f16 FPR16:$Rn), fpimm0)]> {
5920+
[(set NZCV, (OpNode (f16 FPR16:$Rn), fpimm0))]> {
59215921
let Inst{23-22} = 0b11;
59225922
let Predicates = [HasFullFP16];
59235923
}
59245924

59255925
def Srr : BaseTwoOperandFPComparison<signalAllNans, FPR32, asm,
5926-
[(OpNode FPR32:$Rn, (f32 FPR32:$Rm))]> {
5926+
[(set NZCV, (OpNode FPR32:$Rn, (f32 FPR32:$Rm)))]> {
59275927
let Inst{23-22} = 0b00;
59285928
}
59295929

59305930
def Sri : BaseOneOperandFPComparison<signalAllNans, FPR32, asm,
5931-
[(OpNode (f32 FPR32:$Rn), fpimm0)]> {
5931+
[(set NZCV, (OpNode (f32 FPR32:$Rn), fpimm0))]> {
59325932
let Inst{23-22} = 0b00;
59335933
}
59345934

59355935
def Drr : BaseTwoOperandFPComparison<signalAllNans, FPR64, asm,
5936-
[(OpNode FPR64:$Rn, (f64 FPR64:$Rm))]> {
5936+
[(set NZCV, (OpNode FPR64:$Rn, (f64 FPR64:$Rm)))]> {
59375937
let Inst{23-22} = 0b01;
59385938
}
59395939

59405940
def Dri : BaseOneOperandFPComparison<signalAllNans, FPR64, asm,
5941-
[(OpNode (f64 FPR64:$Rn), fpimm0)]> {
5941+
[(set NZCV, (OpNode (f64 FPR64:$Rn), fpimm0))]> {
59425942
let Inst{23-22} = 0b01;
59435943
}
59445944
} // Defs = [NZCV]

‎llvm/lib/Target/AArch64/AArch64InstrInfo.td‎

Lines changed: 8 additions & 7 deletions
Original file line numberDiff line numberDiff line change
@@ -438,9 +438,9 @@ def SDT_AArch64FCCMP : SDTypeProfile<1, 5,
438438
SDTCisInt<3>,
439439
SDTCisInt<4>,
440440
SDTCisVT<5, i32>]>;
441-
def SDT_AArch64FCmp : SDTypeProfile<0, 2,
442-
[SDTCisFP<0>,
443-
SDTCisSameAs<0, 1>]>;
441+
def SDT_AArch64FCmp : SDTypeProfile<1, 2, [SDTCisVT<0, i32>,
442+
SDTCisFP<1>,
443+
SDTCisSameAs<2, 1>]>;
444444
def SDT_AArch64Dup : SDTypeProfile<1, 1, [SDTCisVec<0>]>;
445445
def SDT_AArch64DupLane : SDTypeProfile<1, 2, [SDTCisVec<0>, SDTCisInt<2>]>;
446446
def SDT_AArch64Insr : SDTypeProfile<1, 2, [SDTCisVec<0>]>;
@@ -881,8 +881,7 @@ def AArch64uitof: SDNode<"AArch64ISD::UITOF", SDT_AArch64ITOF>;
881881

882882
def AArch64tlsdesc_callseq : SDNode<"AArch64ISD::TLSDESC_CALLSEQ",
883883
SDT_AArch64TLSDescCallSeq,
884-
[SDNPInGlue, SDNPOutGlue, SDNPHasChain,
885-
SDNPVariadic]>;
884+
[SDNPOutGlue, SDNPHasChain, SDNPVariadic]>;
886885

887886

888887
def AArch64WrapperLarge : SDNode<"AArch64ISD::WrapperLarge",
@@ -992,8 +991,10 @@ def AArch64probedalloca
992991
[SDNPHasChain, SDNPMayStore]>;
993992

994993
def AArch64mrs : SDNode<"AArch64ISD::MRS",
995-
SDTypeProfile<1, 1, [SDTCisVT<0, i64>, SDTCisVT<1, i32>]>,
996-
[SDNPHasChain, SDNPOutGlue]>;
994+
SDTypeProfile<2, 1, [SDTCisVT<0, i64>,
995+
SDTCisVT<1, i32>,
996+
SDTCisVT<2, i32>]>,
997+
[SDNPHasChain]>;
997998

998999
def SD_AArch64rshrnb : SDTypeProfile<1, 2, [SDTCisVec<0>, SDTCisVec<1>, SDTCisInt<2>]>;
9991000
def AArch64rshrnb : SDNode<"AArch64ISD::RSHRNB_I", SD_AArch64rshrnb>;

‎llvm/lib/Target/AArch64/AArch64SVEInstrInfo.td‎

Lines changed: 5 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -376,7 +376,11 @@ def AArch64fadda_p : PatFrags<(ops node:$op1, node:$op2, node:$op3),
376376
(AArch64fadda_p_node (SVEAllActive), node:$op2,
377377
(vselect node:$op1, node:$op3, (splat_vector (f64 fpimm_minus0))))]>;
378378

379-
def SDT_AArch64PTest : SDTypeProfile<0, 2, [SDTCisVec<0>, SDTCisSameAs<0,1>]>;
379+
def SDT_AArch64PTest : SDTypeProfile<1, 2, [
380+
SDTCisVT<0, i32>, // out flags
381+
SDTCisVec<1>, // governing predicate
382+
SDTCisSameAs<2, 1> // source predicate
383+
]>;
380384
def AArch64ptest : SDNode<"AArch64ISD::PTEST", SDT_AArch64PTest>;
381385
def AArch64ptest_any : SDNode<"AArch64ISD::PTEST_ANY", SDT_AArch64PTest>;
382386

‎llvm/lib/Target/AArch64/SVEInstrFormats.td‎

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -836,7 +836,7 @@ class sve_int_ptest<bits<6> opc, string asm, SDPatternOperator op>
836836
: I<(outs), (ins PPRAny:$Pg, PPR8:$Pn),
837837
asm, "\t$Pg, $Pn",
838838
"",
839-
[(op (nxv16i1 PPRAny:$Pg), (nxv16i1 PPR8:$Pn))]>, Sched<[]> {
839+
[(set NZCV, (op (nxv16i1 PPRAny:$Pg), (nxv16i1 PPR8:$Pn)))]>, Sched<[]> {
840840
bits<4> Pg;
841841
bits<4> Pn;
842842
let Inst{31-24} = 0b00100101;
@@ -860,7 +860,7 @@ multiclass sve_int_ptest<bits<6> opc, string asm, SDPatternOperator op,
860860

861861
let hasNoSchedulingInfo = 1, isCompare = 1, Defs = [NZCV] in {
862862
def _ANY : Pseudo<(outs), (ins PPRAny:$Pg, PPR8:$Pn),
863-
[(op_any (nxv16i1 PPRAny:$Pg), (nxv16i1 PPR8:$Pn))]>,
863+
[(set NZCV, (op_any (nxv16i1 PPRAny:$Pg), (nxv16i1 PPR8:$Pn)))]>,
864864
PseudoInstExpansion<(!cast<Instruction>(NAME) PPRAny:$Pg, PPR8:$Pn)>;
865865
}
866866
}

0 commit comments

Comments
 (0)