[GlobalISel] Remove workarounds for cache assertion while adding G_ABS knownbits

Author: r41k0u

llvm/include/llvm/CodeGen/GlobalISel/GISelValueTracking.h

@@ -67,9 +67,6 @@ class LLVM_ABI GISelValueTracking : public GISelChangeObserver {
   void computeKnownBitsImpl(Register R, KnownBits &Known,
                             const APInt &DemandedElts, unsigned Depth = 0);
 
-  virtual unsigned computeNumSignBitsImpl(Register R, const APInt &DemandedElts,
-                                          unsigned Depth = 0);
-
   unsigned computeNumSignBits(Register R, const APInt &DemandedElts,
                               unsigned Depth = 0);
   unsigned computeNumSignBits(Register R, unsigned Depth = 0);

llvm/lib/CodeGen/GlobalISel/GISelValueTracking.cpp

@@ -680,7 +680,7 @@ void GISelValueTracking::computeKnownBitsImpl(Register R, KnownBits &Known,
     computeKnownBitsImpl(SrcReg, Known, DemandedElts, Depth + 1);
     Known = Known.abs();
     Known.Zero.setHighBits(
-        computeNumSignBitsImpl(SrcReg, DemandedElts, Depth + 1) - 1);
+        computeNumSignBits(SrcReg, DemandedElts, Depth + 1) - 1);
     break;
   }
   }
@@ -1731,11 +1731,10 @@ unsigned GISelValueTracking::computeNumSignBitsMin(Register Src0, Register Src1,
                                                    const APInt &DemandedElts,
                                                    unsigned Depth) {
   // Test src1 first, since we canonicalize simpler expressions to the RHS.
-  unsigned Src1SignBits = computeNumSignBitsImpl(Src1, DemandedElts, Depth);
+  unsigned Src1SignBits = computeNumSignBits(Src1, DemandedElts, Depth);
   if (Src1SignBits == 1)
     return 1;
-  return std::min(computeNumSignBitsImpl(Src0, DemandedElts, Depth),
-                  Src1SignBits);
+  return std::min(computeNumSignBits(Src0, DemandedElts, Depth), Src1SignBits);
 }
 
 /// Compute the known number of sign bits with attached range metadata in the
@@ -1765,9 +1764,9 @@ static unsigned computeNumSignBitsFromRangeMetadata(const GAnyLoad *Ld,
                   CR.getSignedMax().getNumSignBits());
 }
 
-unsigned GISelValueTracking::computeNumSignBitsImpl(Register R,
-                                                    const APInt &DemandedElts,
-                                                    unsigned Depth) {
+unsigned GISelValueTracking::computeNumSignBits(Register R,
+						const APInt &DemandedElts,
+                                                unsigned Depth) {
   MachineInstr &MI = *MRI.getVRegDef(R);
   unsigned Opcode = MI.getOpcode();
 
@@ -1797,7 +1796,7 @@ unsigned GISelValueTracking::computeNumSignBitsImpl(Register R,
     if (Src.getReg().isVirtual() && Src.getSubReg() == 0 &&
         MRI.getType(Src.getReg()).isValid()) {
       // Don't increment Depth for this one since we didn't do any work.
-      return computeNumSignBitsImpl(Src.getReg(), DemandedElts, Depth);
+      return computeNumSignBits(Src.getReg(), DemandedElts, Depth);
     }
 
     return 1;
@@ -1806,15 +1805,15 @@ unsigned GISelValueTracking::computeNumSignBitsImpl(Register R,
     Register Src = MI.getOperand(1).getReg();
     LLT SrcTy = MRI.getType(Src);
     unsigned Tmp = DstTy.getScalarSizeInBits() - SrcTy.getScalarSizeInBits();
-    return computeNumSignBitsImpl(Src, DemandedElts, Depth + 1) + Tmp;
+    return computeNumSignBits(Src, DemandedElts, Depth + 1) + Tmp;
   }
   case TargetOpcode::G_ASSERT_SEXT:
   case TargetOpcode::G_SEXT_INREG: {
     // Max of the input and what this extends.
     Register Src = MI.getOperand(1).getReg();
     unsigned SrcBits = MI.getOperand(2).getImm();
     unsigned InRegBits = TyBits - SrcBits + 1;
-    return std::max(computeNumSignBitsImpl(Src, DemandedElts, Depth + 1),
+    return std::max(computeNumSignBits(Src, DemandedElts, Depth + 1),
                     InRegBits);
   }
   case TargetOpcode::G_LOAD: {
@@ -1859,19 +1858,19 @@ unsigned GISelValueTracking::computeNumSignBitsImpl(Register R,
   case TargetOpcode::G_XOR: {
     Register Src1 = MI.getOperand(1).getReg();
     unsigned Src1NumSignBits =
-        computeNumSignBitsImpl(Src1, DemandedElts, Depth + 1);
+        computeNumSignBits(Src1, DemandedElts, Depth + 1);
     if (Src1NumSignBits != 1) {
       Register Src2 = MI.getOperand(2).getReg();
       unsigned Src2NumSignBits =
-          computeNumSignBitsImpl(Src2, DemandedElts, Depth + 1);
+          computeNumSignBits(Src2, DemandedElts, Depth + 1);
       FirstAnswer = std::min(Src1NumSignBits, Src2NumSignBits);
     }
     break;
   }
   case TargetOpcode::G_ASHR: {
     Register Src1 = MI.getOperand(1).getReg();
     Register Src2 = MI.getOperand(2).getReg();
-    FirstAnswer = computeNumSignBitsImpl(Src1, DemandedElts, Depth + 1);
+    FirstAnswer = computeNumSignBits(Src1, DemandedElts, Depth + 1);
     if (auto C = getValidMinimumShiftAmount(Src2, DemandedElts, Depth + 1))
       FirstAnswer = std::min<uint64_t>(FirstAnswer + *C, TyBits);
     break;
@@ -1921,8 +1920,7 @@ unsigned GISelValueTracking::computeNumSignBitsImpl(Register R,
     // Check if the sign bits of source go down as far as the truncated value.
     unsigned DstTyBits = DstTy.getScalarSizeInBits();
     unsigned NumSrcBits = SrcTy.getScalarSizeInBits();
-    unsigned NumSrcSignBits =
-        computeNumSignBitsImpl(Src, DemandedElts, Depth + 1);
+    unsigned NumSrcSignBits = computeNumSignBits(Src, DemandedElts, Depth + 1);
     if (NumSrcSignBits > (NumSrcBits - DstTyBits))
       return NumSrcSignBits - (NumSrcBits - DstTyBits);
     break;
@@ -1982,7 +1980,7 @@ unsigned GISelValueTracking::computeNumSignBitsImpl(Register R,
         continue;
 
       unsigned Tmp2 =
-          computeNumSignBitsImpl(MO.getReg(), SingleDemandedElt, Depth + 1);
+          computeNumSignBits(MO.getReg(), SingleDemandedElt, Depth + 1);
       FirstAnswer = std::min(FirstAnswer, Tmp2);
 
       // If we don't know any bits, early out.
@@ -2004,8 +2002,7 @@ unsigned GISelValueTracking::computeNumSignBitsImpl(Register R,
           DemandedElts.extractBits(NumSubVectorElts, I * NumSubVectorElts);
       if (!DemandedSub)
         continue;
-      unsigned Tmp2 =
-          computeNumSignBitsImpl(MO.getReg(), DemandedSub, Depth + 1);
+      unsigned Tmp2 = computeNumSignBits(MO.getReg(), DemandedSub, Depth + 1);
 
       FirstAnswer = std::min(FirstAnswer, Tmp2);
 
@@ -2026,22 +2023,21 @@ unsigned GISelValueTracking::computeNumSignBitsImpl(Register R,
       return 1;
 
     if (!!DemandedLHS)
-      FirstAnswer = computeNumSignBitsImpl(Src1, DemandedLHS, Depth + 1);
+      FirstAnswer = computeNumSignBits(Src1, DemandedLHS, Depth + 1);
     // If we don't know anything, early out and try computeKnownBits fall-back.
     if (FirstAnswer == 1)
       break;
     if (!!DemandedRHS) {
-      unsigned Tmp2 = computeNumSignBitsImpl(MI.getOperand(2).getReg(),
-                                             DemandedRHS, Depth + 1);
+      unsigned Tmp2 = 
+	computeNumSignBits(MI.getOperand(2).getReg(), DemandedRHS, Depth + 1);
       FirstAnswer = std::min(FirstAnswer, Tmp2);
     }
     break;
   }
   case TargetOpcode::G_SPLAT_VECTOR: {
     // Check if the sign bits of source go down as far as the truncated value.
     Register Src = MI.getOperand(1).getReg();
-    unsigned NumSrcSignBits =
-        computeNumSignBitsImpl(Src, APInt(1, 1), Depth + 1);
+    unsigned NumSrcSignBits = computeNumSignBits(Src, APInt(1, 1), Depth + 1);
     unsigned NumSrcBits = MRI.getType(Src).getSizeInBits();
     if (NumSrcSignBits > (NumSrcBits - TyBits))
       return NumSrcSignBits - (NumSrcBits - TyBits);
@@ -2062,8 +2058,7 @@ unsigned GISelValueTracking::computeNumSignBitsImpl(Register R,
 
   // Finally, if we can prove that the top bits of the result are 0's or 1's,
   // use this information.
-  KnownBits Known;
-  computeKnownBitsImpl(R, Known, DemandedElts, Depth);
+  KnownBits Known = getKnownBits(R, DemandedElts, Depth);
   APInt Mask;
   if (Known.isNonNegative()) { // sign bit is 0
     Mask = Known.Zero;
@@ -2080,15 +2075,6 @@ unsigned GISelValueTracking::computeNumSignBitsImpl(Register R,
   return std::max(FirstAnswer, Mask.countl_one());
 }
 
-unsigned GISelValueTracking::computeNumSignBits(Register R,
-                                                const APInt &DemandedElts,
-                                                unsigned Depth) {
-  assert(ComputeKnownBitsCache.empty() && "Cache should be empty");
-  unsigned NumSignBits = computeNumSignBitsImpl(R, DemandedElts, Depth);
-  ComputeKnownBitsCache.clear();
-  return NumSignBits;
-}
-
 unsigned GISelValueTracking::computeNumSignBits(Register R, unsigned Depth) {
   LLT Ty = MRI.getType(R);
   APInt DemandedElts =
@@ -2139,8 +2125,7 @@ std::optional<ConstantRange> GISelValueTracking::getValidShiftAmountRange(
 
   // Use computeKnownBits to find a hidden constant/knownbits (usually type
   // legalized). e.g. Hidden behind multiple bitcasts/build_vector/casts etc.
-  KnownBits KnownAmt;
-  computeKnownBitsImpl(R, KnownAmt, DemandedElts, Depth);
+  KnownBits KnownAmt = getKnownBits(R, DemandedElts, Depth);
   if (KnownAmt.getMaxValue().ult(BitWidth))
     return ConstantRange::fromKnownBits(KnownAmt, /*IsSigned=*/false);
 

llvm/lib/Target/AMDGPU/AMDGPUISelLowering.cpp

@@ -6139,16 +6139,13 @@ unsigned AMDGPUTargetLowering::computeNumSignBitsForTargetInstr(
   case AMDGPU::G_AMDGPU_SMED3:
   case AMDGPU::G_AMDGPU_UMED3: {
     auto [Dst, Src0, Src1, Src2] = MI->getFirst4Regs();
-    unsigned Tmp2 =
-        Analysis.computeNumSignBitsImpl(Src2, DemandedElts, Depth + 1);
+    unsigned Tmp2 = Analysis.computeNumSignBits(Src2, DemandedElts, Depth + 1);
     if (Tmp2 == 1)
       return 1;
-    unsigned Tmp1 =
-        Analysis.computeNumSignBitsImpl(Src1, DemandedElts, Depth + 1);
+    unsigned Tmp1 = Analysis.computeNumSignBits(Src1, DemandedElts, Depth + 1);
     if (Tmp1 == 1)
       return 1;
-    unsigned Tmp0 =
-        Analysis.computeNumSignBitsImpl(Src0, DemandedElts, Depth + 1);
+    unsigned Tmp0 = Analysis.computeNumSignBits(Src0, DemandedElts, Depth + 1);
     if (Tmp0 == 1)
       return 1;
     return std::min({Tmp0, Tmp1, Tmp2});