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[RISCV][GISel] Slightly simplify the regbank selection for G_LOAD/STORE. NFC (#101431)
Merge the isVector early out with the previous check for isVector.
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llvm/lib/Target/RISCV/GISel/RISCVRegisterBankInfo.cpp

Lines changed: 11 additions & 10 deletions
Original file line numberDiff line numberDiff line change
@@ -311,15 +311,16 @@ RISCVRegisterBankInfo::getInstrMapping(const MachineInstr &MI) const {
311311
case TargetOpcode::G_LOAD: {
312312
LLT Ty = MRI.getType(MI.getOperand(0).getReg());
313313
TypeSize Size = Ty.getSizeInBits();
314-
if (Ty.isVector())
315-
OpdsMapping[0] = getVRBValueMapping(Size.getKnownMinValue());
316-
else
317-
OpdsMapping[0] = GPRValueMapping;
318314

319315
OpdsMapping[1] = GPRValueMapping;
320316

321-
if (Ty.isVector())
317+
if (Ty.isVector()) {
318+
OpdsMapping[0] = getVRBValueMapping(Size.getKnownMinValue());
322319
break;
320+
}
321+
322+
OpdsMapping[0] = GPRValueMapping;
323+
323324
// Use FPR64 for s64 loads on rv32.
324325
if (GPRSize == 32 && Size.getFixedValue() == 64) {
325326
assert(MF.getSubtarget<RISCVSubtarget>().hasStdExtD());
@@ -342,15 +343,15 @@ RISCVRegisterBankInfo::getInstrMapping(const MachineInstr &MI) const {
342343
case TargetOpcode::G_STORE: {
343344
LLT Ty = MRI.getType(MI.getOperand(0).getReg());
344345
TypeSize Size = Ty.getSizeInBits();
345-
if (Ty.isVector())
346-
OpdsMapping[0] = getVRBValueMapping(Size.getKnownMinValue());
347-
else
348-
OpdsMapping[0] = GPRValueMapping;
349346

350347
OpdsMapping[1] = GPRValueMapping;
351348

352-
if (Ty.isVector())
349+
if (Ty.isVector()) {
350+
OpdsMapping[0] = getVRBValueMapping(Size.getKnownMinValue());
353351
break;
352+
}
353+
354+
OpdsMapping[0] = GPRValueMapping;
354355

355356
// Use FPR64 for s64 stores on rv32.
356357
if (GPRSize == 32 && Size.getFixedValue() == 64) {

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