fixup! Remove the PostRAScheduler field

mshockwave · mshockwave · commit a227b3368104 · 2025-05-13T09:22:04.000-07:00
diff --git a/llvm/lib/Target/RISCV/RISCVSchedSiFiveP800.td b/llvm/lib/Target/RISCV/RISCVSchedSiFiveP800.td
@@ -63,7 +63,6 @@ def SiFiveP800Model : SchedMachineModel {
   let MicroOpBufferSize = 288; // Max micro-ops that can be buffered.
   let LoadLatency = 4;         // Cycles for loads to access the cache.
   let MispredictPenalty = 9;   // Extra cycles for a mispredicted branch.
-  let PostRAScheduler = true;
   let UnsupportedFeatures = [HasStdExtZbkb, HasStdExtZbkc, HasStdExtZbkx,
                              HasStdExtZknd, HasStdExtZkne, HasStdExtZknh,
                              HasStdExtZksed, HasStdExtZksh, HasStdExtZkr,
