address comments

Author: AlexMaclean

llvm/lib/Target/NVPTX/NVPTXISelDAGToDAG.cpp

@@ -172,7 +172,7 @@ void NVPTXDAGToDAGISel::Select(SDNode *N) {
   }
   case NVPTXISD::ATOMIC_CMP_SWAP_B128:
   case NVPTXISD::ATOMIC_SWAP_B128:
-    selectAtomic128(N);
+    selectAtomicSwap128(N);
     return;
   case ISD::FADD:
   case ISD::FMUL:
@@ -2342,7 +2342,7 @@ bool NVPTXDAGToDAGISel::tryIntrinsicVoid(SDNode *N) {
   }
 }
 
-void NVPTXDAGToDAGISel::selectAtomic128(SDNode *N) {
+void NVPTXDAGToDAGISel::selectAtomicSwap128(SDNode *N) {
   MemSDNode *AN = cast<MemSDNode>(N);
   SDLoc dl(N);
 

llvm/lib/Target/NVPTX/NVPTXISelDAGToDAG.h

@@ -90,7 +90,7 @@ class LLVM_LIBRARY_VISIBILITY NVPTXDAGToDAGISel : public SelectionDAGISel {
                                            bool IsIm2Col = false);
   void SelectTcgen05Ld(SDNode *N, bool hasOffset = false);
   void SelectTcgen05St(SDNode *N, bool hasOffset = false);
-  void selectAtomic128(SDNode *N);
+  void selectAtomicSwap128(SDNode *N);
 
   inline SDValue getI32Imm(unsigned Imm, const SDLoc &DL) {
     return CurDAG->getTargetConstant(Imm, DL, MVT::i32);

llvm/lib/Target/NVPTX/NVPTXISelLowering.cpp

@@ -6242,7 +6242,7 @@ static void replaceProxyReg(SDNode *N, SelectionDAG &DAG,
   Results.push_back(Res);
 }
 
-static void replaceAtomic128(SDNode *N, SelectionDAG &DAG,
+static void replaceAtomicSwap128(SDNode *N, SelectionDAG &DAG,
                              const NVPTXSubtarget &STI,
                              SmallVectorImpl<SDValue> &Results) {
   assert(N->getValueType(0) == MVT::i128 &&
@@ -6251,7 +6251,7 @@ static void replaceAtomic128(SDNode *N, SelectionDAG &DAG,
   AtomicSDNode *AN = cast<AtomicSDNode>(N);
   SDLoc dl(N);
 
-  if (STI.getSmVersion() < 90 || STI.getPTXVersion() < 83) {
+  if (!STI.hasAtomSwap128()) {
     DAG.getContext()->diagnose(DiagnosticInfoUnsupported(
         DAG.getMachineFunction().getFunction(),
         "Support for b128 atomics introduced in PTX ISA version 8.3 and "
@@ -6307,7 +6307,7 @@ void NVPTXTargetLowering::ReplaceNodeResults(
     return;
   case ISD::ATOMIC_CMP_SWAP:
   case ISD::ATOMIC_SWAP:
-    replaceAtomic128(N, DAG, STI, Results);
+    replaceAtomicSwap128(N, DAG, STI, Results);
     return;
   }
 }

llvm/lib/Target/NVPTX/NVPTXInstrInfo.td

@@ -104,6 +104,7 @@ def hasAtomAddF64 : Predicate<"Subtarget->hasAtomAddF64()">;
 def hasAtomScope : Predicate<"Subtarget->hasAtomScope()">;
 def hasAtomBitwise64 : Predicate<"Subtarget->hasAtomBitwise64()">;
 def hasAtomMinMax64 : Predicate<"Subtarget->hasAtomMinMax64()">;
+def hasAtomSwap128 : Predicate<"Subtarget->hasAtomSwap128()">;
 def hasClusters : Predicate<"Subtarget->hasClusters()">;
 def hasPTXASUnreachableBug : Predicate<"Subtarget->hasPTXASUnreachableBug()">;
 def noPTXASUnreachableBug : Predicate<"!Subtarget->hasPTXASUnreachableBug()">;

llvm/lib/Target/NVPTX/NVPTXIntrinsics.td

@@ -2206,17 +2206,18 @@ defm INT_PTX_SATOM_XOR  : ATOM2_bitwise_impl<"xor">;
 
 // atom.*.b128
 
-let mayLoad = 1, mayStore = 1, hasSideEffects = 1 in {
+let mayLoad = true, mayStore = true, hasSideEffects = true,
+    Predicates = [hasAtomSwap128] in {
   def ATOM_CAS_B128 :
     NVPTXInst<
         (outs B64:$dst0, B64:$dst1),
         (ins ADDR:$addr, B64:$cmp0, B64:$cmp1, B64:$swap0, B64:$swap1,
              AtomicCode:$sem, AtomicCode:$scope, AtomicCode:$addsp),
         "{{\n\t"
-        ".reg .b128 src1, src2, dst;\n\t"
-        "mov.b128 src1, {$cmp0, $cmp1};\n\t"
-        "mov.b128 src2, {$swap0, $swap1};\n\t"
-        "atom${sem:sem}${scope:scope}${addsp:addsp}.cas.b128 dst, $addr, src1, src2;\n\t"
+        ".reg .b128 cmp, swap, dst;\n\t"
+        "mov.b128 cmp, {$cmp0, $cmp1};\n\t"
+        "mov.b128 swap, {$swap0, $swap1};\n\t"
+        "atom${sem:sem}${scope:scope}${addsp:addsp}.cas.b128 dst, [$addr], cmp, swap;\n\t"
         "mov.b128 {$dst0, $dst1}, dst;\n\t"
         "}}">;
 
@@ -2226,9 +2227,9 @@ let mayLoad = 1, mayStore = 1, hasSideEffects = 1 in {
         (ins ADDR:$addr, B64:$amt0, B64:$amt1,
              AtomicCode:$sem, AtomicCode:$scope, AtomicCode:$addsp),
         "{{\n\t"
-        ".reg .b128 src1, dst;\n\t"
-        "mov.b128 src1, {$amt0, $amt1};\n\t"
-        "atom${sem:sem}${scope:scope}${addsp:addsp}.exch.b128 dst, $addr, src1;\n\t"
+        ".reg .b128 amt, dst;\n\t"
+        "mov.b128 amt, {$amt0, $amt1};\n\t"
+        "atom${sem:sem}${scope:scope}${addsp:addsp}.exch.b128 dst, [$addr], amt;\n\t"
         "mov.b128 {$dst0, $dst1}, dst;\n\t"
         "}}">;
 }

llvm/lib/Target/NVPTX/NVPTXSubtarget.h

@@ -82,6 +82,7 @@ class NVPTXSubtarget : public NVPTXGenSubtargetInfo {
   bool hasAtomBitwise64() const { return SmVersion >= 32; }
   bool hasAtomMinMax64() const { return SmVersion >= 32; }
   bool hasAtomCas16() const { return SmVersion >= 70 && PTXVersion >= 63; }
+  bool hasAtomSwap128() const { return SmVersion >= 90 && PTXVersion >= 83; }
   bool hasClusters() const { return SmVersion >= 90 && PTXVersion >= 78; }
   bool hasLDG() const { return SmVersion >= 32; }
   bool hasHWROT32() const { return SmVersion >= 32; }