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1 parent 904641f commit a255f16Copy full SHA for a255f16
llvm/test/CodeGen/RISCV/stores-of-loads-merging.ll
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; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc < %s -mtriple=riscv64 -mattr=+v | FileCheck %s
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-declare i32 @llvm.experimental.constrained.fptosi.i32.f64(double, metadata)
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declare void @g()
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; TODO: Merging scalars into vectors is unprofitable because we have no
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