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[RISCV] Remove unnecessary entries from RISCVVInversePseudosTable. NFC
The inverse pseudos table contained entries that map back to the unmasked and masked pseudo, but the lookup only returns the first one. Add a new class so we can control which instructions have an inverse in the table. This reduces the size of the llvm-mca binary by ~32KB.
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-41
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3 files changed

+44
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‎llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td‎

Lines changed: 36 additions & 33 deletions
Original file line numberDiff line numberDiff line change
@@ -557,6 +557,9 @@ class RISCVVPseudo {
557557
bit NeedBeInPseudoTable = 1;
558558
}
559559

560+
// Class to filter for the RISCVVInversePseudosTable.
561+
class RISCVVPseudoInverse : RISCVVPseudo;
562+
560563
// The actual table.
561564
def RISCVVPseudosTable : GenericTable {
562565
let FilterClass = "RISCVVPseudo";
@@ -569,7 +572,7 @@ def RISCVVPseudosTable : GenericTable {
569572
}
570573

571574
def RISCVVInversePseudosTable : GenericTable {
572-
let FilterClass = "RISCVVPseudo";
575+
let FilterClass = "RISCVVPseudoInverse";
573576
let CppTypeName = "PseudoInfo";
574577
let Fields = [ "Pseudo", "BaseInstr", "VLMul", "SEW"];
575578
let PrimaryKey = [ "BaseInstr", "VLMul", "SEW"];
@@ -785,7 +788,7 @@ class VPseudoUSLoadNoMask<VReg RetClass,
785788
Pseudo<(outs RetClass:$rd),
786789
(ins RetClass:$dest, GPRMem:$rs1, AVL:$vl, sewop:$sew,
787790
vec_policy:$policy), []>,
788-
RISCVVPseudo,
791+
RISCVVPseudoInverse,
789792
RISCVVLE</*Masked*/0, /*Strided*/0, /*FF*/0, !logtwo(EEW), VLMul> {
790793
let mayLoad = 1;
791794
let mayStore = 0;
@@ -819,7 +822,7 @@ class VPseudoUSLoadFFNoMask<VReg RetClass,
819822
Pseudo<(outs RetClass:$rd, GPR:$vl),
820823
(ins RetClass:$dest, GPRMem:$rs1, AVL:$avl,
821824
sew:$sew, vec_policy:$policy), []>,
822-
RISCVVPseudo,
825+
RISCVVPseudoInverse,
823826
RISCVVLE</*Masked*/0, /*Strided*/0, /*FF*/1, !logtwo(EEW), VLMul> {
824827
let mayLoad = 1;
825828
let mayStore = 0;
@@ -853,7 +856,7 @@ class VPseudoSLoadNoMask<VReg RetClass,
853856
Pseudo<(outs RetClass:$rd),
854857
(ins RetClass:$dest, GPRMem:$rs1, GPR:$rs2, AVL:$vl,
855858
sew:$sew, vec_policy:$policy), []>,
856-
RISCVVPseudo,
859+
RISCVVPseudoInverse,
857860
RISCVVLE</*Masked*/0, /*Strided*/1, /*FF*/0, !logtwo(EEW), VLMul> {
858861
let mayLoad = 1;
859862
let mayStore = 0;
@@ -892,7 +895,7 @@ class VPseudoILoadNoMask<VReg RetClass,
892895
Pseudo<(outs RetClass:$rd),
893896
(ins RetClass:$dest, GPRMem:$rs1, IdxClass:$rs2, AVL:$vl,
894897
sew:$sew, vec_policy:$policy), []>,
895-
RISCVVPseudo,
898+
RISCVVPseudoInverse,
896899
RISCVVLX</*Masked*/0, Ordered, !logtwo(EEW), VLMul, LMUL> {
897900
let mayLoad = 1;
898901
let mayStore = 0;
@@ -933,7 +936,7 @@ class VPseudoUSStoreNoMask<VReg StClass,
933936
DAGOperand sewop = sew> :
934937
Pseudo<(outs),
935938
(ins StClass:$rd, GPRMem:$rs1, AVL:$vl, sewop:$sew), []>,
936-
RISCVVPseudo,
939+
RISCVVPseudoInverse,
937940
RISCVVSE</*Masked*/0, /*Strided*/0, !logtwo(EEW), VLMul> {
938941
let mayLoad = 0;
939942
let mayStore = 1;
@@ -961,7 +964,7 @@ class VPseudoSStoreNoMask<VReg StClass,
961964
Pseudo<(outs),
962965
(ins StClass:$rd, GPRMem:$rs1, GPR:$rs2,
963966
AVL:$vl, sew:$sew), []>,
964-
RISCVVPseudo,
967+
RISCVVPseudoInverse,
965968
RISCVVSE</*Masked*/0, /*Strided*/1, !logtwo(EEW), VLMul> {
966969
let mayLoad = 0;
967970
let mayStore = 1;
@@ -988,7 +991,7 @@ class VPseudoNullaryNoMask<VReg RegClass> :
988991
Pseudo<(outs RegClass:$rd),
989992
(ins RegClass:$passthru,
990993
AVL:$vl, sew:$sew, vec_policy:$policy), []>,
991-
RISCVVPseudo {
994+
RISCVVPseudoInverse {
992995
let mayLoad = 0;
993996
let mayStore = 0;
994997
let hasSideEffects = 0;
@@ -1037,7 +1040,7 @@ class VPseudoUnaryNoMask<DAGOperand RetClass,
10371040
Pseudo<(outs RetClass:$rd),
10381041
(ins RetClass:$passthru, OpClass:$rs2,
10391042
AVL:$vl, sew:$sew, vec_policy:$policy), []>,
1040-
RISCVVPseudo {
1043+
RISCVVPseudoInverse {
10411044
let mayLoad = 0;
10421045
let mayStore = 0;
10431046
let hasSideEffects = 0;
@@ -1054,7 +1057,7 @@ class VPseudoUnaryNoMaskNoPolicy<DAGOperand RetClass,
10541057
bits<2> TargetConstraintType = 1> :
10551058
Pseudo<(outs RetClass:$rd),
10561059
(ins OpClass:$rs2, AVL:$vl, sew_mask:$sew), []>,
1057-
RISCVVPseudo {
1060+
RISCVVPseudoInverse {
10581061
let mayLoad = 0;
10591062
let mayStore = 0;
10601063
let hasSideEffects = 0;
@@ -1071,7 +1074,7 @@ class VPseudoUnaryNoMaskRoundingMode<DAGOperand RetClass,
10711074
Pseudo<(outs RetClass:$rd),
10721075
(ins RetClass:$passthru, OpClass:$rs2, vec_rm:$rm,
10731076
AVL:$vl, sew:$sew, vec_policy:$policy), []>,
1074-
RISCVVPseudo {
1077+
RISCVVPseudoInverse {
10751078
let mayLoad = 0;
10761079
let mayStore = 0;
10771080
let hasSideEffects = 0;
@@ -1148,7 +1151,7 @@ class VPseudoUnaryMask_NoExcept<VReg RetClass,
11481151
class VPseudoUnaryNoMaskGPROut :
11491152
Pseudo<(outs GPR:$rd),
11501153
(ins VR:$rs2, AVL:$vl, sew_mask:$sew), []>,
1151-
RISCVVPseudo {
1154+
RISCVVPseudoInverse {
11521155
let mayLoad = 0;
11531156
let mayStore = 0;
11541157
let hasSideEffects = 0;
@@ -1173,7 +1176,7 @@ class VPseudoUnaryAnyMask<VReg RetClass,
11731176
Pseudo<(outs RetClass:$rd),
11741177
(ins RetClass:$passthru, Op1Class:$rs2,
11751178
VR:$vm, AVL:$vl, sew:$sew), []>,
1176-
RISCVVPseudo {
1179+
RISCVVPseudoInverse {
11771180
let mayLoad = 0;
11781181
let mayStore = 0;
11791182
let hasSideEffects = 0;
@@ -1190,7 +1193,7 @@ class VPseudoBinaryNoMask<VReg RetClass,
11901193
DAGOperand sewop = sew> :
11911194
Pseudo<(outs RetClass:$rd),
11921195
(ins Op1Class:$rs2, Op2Class:$rs1, AVL:$vl, sewop:$sew), []>,
1193-
RISCVVPseudo {
1196+
RISCVVPseudoInverse {
11941197
let mayLoad = 0;
11951198
let mayStore = 0;
11961199
let hasSideEffects = 0;
@@ -1208,7 +1211,7 @@ class VPseudoBinaryNoMaskPolicy<VReg RetClass,
12081211
Pseudo<(outs RetClass:$rd),
12091212
(ins RetClass:$passthru, Op1Class:$rs2, Op2Class:$rs1, AVL:$vl,
12101213
sew:$sew, vec_policy:$policy), []>,
1211-
RISCVVPseudo {
1214+
RISCVVPseudoInverse {
12121215
let mayLoad = 0;
12131216
let mayStore = 0;
12141217
let hasSideEffects = 0;
@@ -1228,7 +1231,7 @@ class VPseudoBinaryNoMaskRoundingMode<VReg RetClass,
12281231
Pseudo<(outs RetClass:$rd),
12291232
(ins RetClass:$passthru, Op1Class:$rs2, Op2Class:$rs1, vec_rm:$rm,
12301233
AVL:$vl, sew:$sew, vec_policy:$policy), []>,
1231-
RISCVVPseudo {
1234+
RISCVVPseudoInverse {
12321235
let mayLoad = 0;
12331236
let mayStore = 0;
12341237
let Constraints = !interleave([Constraint, "$rd = $passthru"], ",");
@@ -1319,7 +1322,7 @@ class VPseudoIStoreNoMask<VReg StClass, VReg IdxClass, int EEW, bits<3> LMUL,
13191322
Pseudo<(outs),
13201323
(ins StClass:$rd, GPRMem:$rs1, IdxClass:$rs2, AVL:$vl,
13211324
sew:$sew),[]>,
1322-
RISCVVPseudo,
1325+
RISCVVPseudoInverse,
13231326
RISCVVSX</*Masked*/0, Ordered, !logtwo(EEW), VLMul, LMUL> {
13241327
let mayLoad = 0;
13251328
let mayStore = 1;
@@ -1487,7 +1490,7 @@ class VPseudoBinaryCarry<VReg RetClass,
14871490
VMV0:$carry, AVL:$vl, sew:$sew),
14881491
(ins Op1Class:$rs2, Op2Class:$rs1,
14891492
AVL:$vl, sew:$sew)), []>,
1490-
RISCVVPseudo {
1493+
RISCVVPseudoInverse {
14911494
let mayLoad = 0;
14921495
let mayStore = 0;
14931496
let hasSideEffects = 0;
@@ -1506,7 +1509,7 @@ class VPseudoTiedBinaryCarryIn<VReg RetClass,
15061509
Pseudo<(outs RetClass:$rd),
15071510
(ins RetClass:$passthru, Op1Class:$rs2, Op2Class:$rs1,
15081511
VMV0:$carry, AVL:$vl, sew:$sew), []>,
1509-
RISCVVPseudo {
1512+
RISCVVPseudoInverse {
15101513
let mayLoad = 0;
15111514
let mayStore = 0;
15121515
let hasSideEffects = 0;
@@ -1525,7 +1528,7 @@ class VPseudoTernaryNoMask<VReg RetClass,
15251528
Pseudo<(outs RetClass:$rd),
15261529
(ins RetClass:$rs3, Op1Class:$rs1, Op2Class:$rs2,
15271530
AVL:$vl, sew:$sew), []>,
1528-
RISCVVPseudo {
1531+
RISCVVPseudoInverse {
15291532
let mayLoad = 0;
15301533
let mayStore = 0;
15311534
let hasSideEffects = 0;
@@ -1542,7 +1545,7 @@ class VPseudoTernaryNoMaskWithPolicy<VReg RetClass,
15421545
Pseudo<(outs RetClass:$rd),
15431546
(ins RetClass:$rs3, Op1Class:$rs1, Op2Class:$rs2,
15441547
AVL:$vl, sew:$sew, vec_policy:$policy), []>,
1545-
RISCVVPseudo {
1548+
RISCVVPseudoInverse {
15461549
let mayLoad = 0;
15471550
let mayStore = 0;
15481551
let hasSideEffects = 0;
@@ -1561,7 +1564,7 @@ class VPseudoTernaryNoMaskWithPolicyRoundingMode<VReg RetClass,
15611564
Pseudo<(outs RetClass:$rd),
15621565
(ins RetClass:$rs3, Op1Class:$rs1, Op2Class:$rs2,
15631566
vec_rm:$rm, AVL:$vl, sew:$sew, vec_policy:$policy), []>,
1564-
RISCVVPseudo {
1567+
RISCVVPseudoInverse {
15651568
let mayLoad = 0;
15661569
let mayStore = 0;
15671570
let hasSideEffects = 0;
@@ -1581,7 +1584,7 @@ class VPseudoUSSegLoadNoMask<VReg RetClass,
15811584
Pseudo<(outs RetClass:$rd),
15821585
(ins RetClass:$dest, GPRMem:$rs1, AVL:$vl,
15831586
sew:$sew, vec_policy:$policy), []>,
1584-
RISCVVPseudo,
1587+
RISCVVPseudoInverse,
15851588
RISCVVLSEG<NF, /*Masked*/0, /*Strided*/0, /*FF*/0, !logtwo(EEW), VLMul> {
15861589
let mayLoad = 1;
15871590
let mayStore = 0;
@@ -1616,7 +1619,7 @@ class VPseudoUSSegLoadFFNoMask<VReg RetClass,
16161619
Pseudo<(outs RetClass:$rd, GPR:$vl),
16171620
(ins RetClass:$dest, GPRMem:$rs1, AVL:$avl,
16181621
sew:$sew, vec_policy:$policy), []>,
1619-
RISCVVPseudo,
1622+
RISCVVPseudoInverse,
16201623
RISCVVLSEG<NF, /*Masked*/0, /*Strided*/0, /*FF*/1, !logtwo(EEW), VLMul> {
16211624
let mayLoad = 1;
16221625
let mayStore = 0;
@@ -1651,7 +1654,7 @@ class VPseudoSSegLoadNoMask<VReg RetClass,
16511654
Pseudo<(outs RetClass:$rd),
16521655
(ins RetClass:$passthru, GPRMem:$rs1, GPR:$offset, AVL:$vl,
16531656
sew:$sew, vec_policy:$policy), []>,
1654-
RISCVVPseudo,
1657+
RISCVVPseudoInverse,
16551658
RISCVVLSEG<NF, /*Masked*/0, /*Strided*/1, /*FF*/0, !logtwo(EEW), VLMul> {
16561659
let mayLoad = 1;
16571660
let mayStore = 0;
@@ -1690,7 +1693,7 @@ class VPseudoISegLoadNoMask<VReg RetClass,
16901693
Pseudo<(outs RetClass:$rd),
16911694
(ins RetClass:$passthru, GPRMem:$rs1, IdxClass:$offset, AVL:$vl,
16921695
sew:$sew, vec_policy:$policy), []>,
1693-
RISCVVPseudo,
1696+
RISCVVPseudoInverse,
16941697
RISCVVLXSEG<NF, /*Masked*/0, Ordered, !logtwo(EEW), VLMul, LMUL> {
16951698
let mayLoad = 1;
16961699
let mayStore = 0;
@@ -1732,7 +1735,7 @@ class VPseudoUSSegStoreNoMask<VReg ValClass,
17321735
bits<4> NF> :
17331736
Pseudo<(outs),
17341737
(ins ValClass:$rd, GPRMem:$rs1, AVL:$vl, sew:$sew), []>,
1735-
RISCVVPseudo,
1738+
RISCVVPseudoInverse,
17361739
RISCVVSSEG<NF, /*Masked*/0, /*Strided*/0, !logtwo(EEW), VLMul> {
17371740
let mayLoad = 0;
17381741
let mayStore = 1;
@@ -1762,7 +1765,7 @@ class VPseudoSSegStoreNoMask<VReg ValClass,
17621765
Pseudo<(outs),
17631766
(ins ValClass:$rd, GPRMem:$rs1, GPR:$offset,
17641767
AVL:$vl, sew:$sew), []>,
1765-
RISCVVPseudo,
1768+
RISCVVPseudoInverse,
17661769
RISCVVSSEG<NF, /*Masked*/0, /*Strided*/1, !logtwo(EEW), VLMul> {
17671770
let mayLoad = 0;
17681771
let mayStore = 1;
@@ -1795,7 +1798,7 @@ class VPseudoISegStoreNoMask<VReg ValClass,
17951798
Pseudo<(outs),
17961799
(ins ValClass:$rd, GPRMem:$rs1, IdxClass: $index,
17971800
AVL:$vl, sew:$sew), []>,
1798-
RISCVVPseudo,
1801+
RISCVVPseudoInverse,
17991802
RISCVVSXSEG<NF, /*Masked*/0, Ordered, !logtwo(EEW), VLMul, LMUL> {
18001803
let mayLoad = 0;
18011804
let mayStore = 1;
@@ -6680,14 +6683,14 @@ let mayLoad = 0, mayStore = 0, hasSideEffects = 0 in {
66806683
def PseudoVMV_X_S:
66816684
Pseudo<(outs GPR:$rd), (ins VR:$rs2, sew:$sew), []>,
66826685
Sched<[WriteVMovXS, ReadVMovXS]>,
6683-
RISCVVPseudo;
6686+
RISCVVPseudoInverse;
66846687
let HasVLOp = 1, HasSEWOp = 1, BaseInstr = VMV_S_X, isReMaterializable = 1,
66856688
Constraints = "$rd = $rs1" in
66866689
def PseudoVMV_S_X: Pseudo<(outs VR:$rd),
66876690
(ins VR:$rs1, GPR:$rs2, AVL:$vl, sew:$sew),
66886691
[]>,
66896692
Sched<[WriteVMovSX, ReadVMovSX_V, ReadVMovSX_X]>,
6690-
RISCVVPseudo;
6693+
RISCVVPseudoInverse;
66916694
}
66926695
} // Predicates = [HasVInstructions]
66936696

@@ -6703,15 +6706,15 @@ let mayLoad = 0, mayStore = 0, hasSideEffects = 0 in {
67036706
Pseudo<(outs f.fprclass:$rd),
67046707
(ins VR:$rs2, sew:$sew), []>,
67056708
Sched<[WriteVMovFS, ReadVMovFS]>,
6706-
RISCVVPseudo;
6709+
RISCVVPseudoInverse;
67076710
let HasVLOp = 1, HasSEWOp = 1, BaseInstr = VFMV_S_F, isReMaterializable = 1,
67086711
Constraints = "$rd = $rs1" in
67096712
def "PseudoVFMV_S_" # f.FX :
67106713
Pseudo<(outs VR:$rd),
67116714
(ins VR:$rs1, f.fprclass:$rs2, AVL:$vl, sew:$sew),
67126715
[]>,
67136716
Sched<[WriteVMovSF, ReadVMovSF_V, ReadVMovSF_F]>,
6714-
RISCVVPseudo;
6717+
RISCVVPseudoInverse;
67156718
}
67166719
}
67176720
} // Predicates = [HasVInstructionsAnyF]

‎llvm/lib/Target/RISCV/RISCVInstrInfoXSf.td‎

Lines changed: 6 additions & 6 deletions
Original file line numberDiff line numberDiff line change
@@ -232,7 +232,7 @@ class VPseudoVC_X<Operand OpClass, DAGOperand RS1Class> :
232232
Pseudo<(outs),
233233
(ins OpClass:$op1, payload5:$rs2, payload5:$rd, RS1Class:$r1,
234234
AVL:$vl, sew:$sew), []>,
235-
RISCVVPseudo {
235+
RISCVVPseudoInverse {
236236
let mayLoad = 0;
237237
let mayStore = 0;
238238
let HasVLOp = 1;
@@ -244,7 +244,7 @@ class VPseudoVC_XV<Operand OpClass, VReg RS2Class, DAGOperand RS1Class> :
244244
Pseudo<(outs),
245245
(ins OpClass:$op1, payload5:$rd, RS2Class:$rs2, RS1Class:$r1,
246246
AVL:$vl, sew:$sew), []>,
247-
RISCVVPseudo {
247+
RISCVVPseudoInverse {
248248
let mayLoad = 0;
249249
let mayStore = 0;
250250
let HasVLOp = 1;
@@ -257,7 +257,7 @@ class VPseudoVC_XVV<Operand OpClass, VReg RDClass, VReg RS2Class,
257257
Pseudo<(outs),
258258
(ins OpClass:$op1, RDClass:$rd, RS2Class:$rs2, RS1Class:$r1,
259259
AVL:$vl, sew:$sew), []>,
260-
RISCVVPseudo {
260+
RISCVVPseudoInverse {
261261
let mayLoad = 0;
262262
let mayStore = 0;
263263
let HasVLOp = 1;
@@ -269,7 +269,7 @@ class VPseudoVC_V_X<Operand OpClass, VReg RDClass, DAGOperand RS1Class> :
269269
Pseudo<(outs RDClass:$rd),
270270
(ins OpClass:$op1, payload5:$rs2, RS1Class:$r1,
271271
AVL:$vl, sew:$sew), []>,
272-
RISCVVPseudo {
272+
RISCVVPseudoInverse {
273273
let mayLoad = 0;
274274
let mayStore = 0;
275275
let HasVLOp = 1;
@@ -282,7 +282,7 @@ class VPseudoVC_V_XV<Operand OpClass, VReg RDClass, VReg RS2Class,
282282
Pseudo<(outs RDClass:$rd),
283283
(ins OpClass:$op1, RS2Class:$rs2, RS1Class:$r1,
284284
AVL:$vl, sew:$sew), []>,
285-
RISCVVPseudo {
285+
RISCVVPseudoInverse {
286286
let mayLoad = 0;
287287
let mayStore = 0;
288288
let HasVLOp = 1;
@@ -295,7 +295,7 @@ class VPseudoVC_V_XVV<Operand OpClass, VReg RDClass, VReg RS2Class,
295295
Pseudo<(outs RDClass:$rd),
296296
(ins OpClass:$op1, RDClass:$rs3, RS2Class:$rs2, RS1Class:$r1,
297297
AVL:$vl, sew:$sew), []>,
298-
RISCVVPseudo {
298+
RISCVVPseudoInverse {
299299
let mayLoad = 0;
300300
let mayStore = 0;
301301
let HasVLOp = 1;

‎llvm/lib/Target/RISCV/RISCVInstrInfoZvk.td‎

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -232,7 +232,7 @@ class ZvkMxSet<string vd_lmul> {
232232
class VPseudoBinaryNoMask_Zvk<DAGOperand RetClass, VReg OpClass> :
233233
Pseudo<(outs RetClass:$rd_wb),
234234
(ins RetClass:$rd, OpClass:$rs2, AVL:$vl, sew:$sew, vec_policy:$policy), []>,
235-
RISCVVPseudo {
235+
RISCVVPseudoInverse {
236236
let mayLoad = 0;
237237
let mayStore = 0;
238238
let hasSideEffects = 0;
@@ -249,7 +249,7 @@ class VPseudoTernaryNoMask_Zvk<VReg RetClass,
249249
Pseudo<(outs RetClass:$rd_wb),
250250
(ins RetClass:$rd, Op1Class:$rs2, Op2Class:$rs1,
251251
AVL:$vl, sew:$sew, vec_policy:$policy), []>,
252-
RISCVVPseudo {
252+
RISCVVPseudoInverse {
253253
let mayLoad = 0;
254254
let mayStore = 0;
255255
let hasSideEffects = 0;

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