[MachineCopyPropagation] Remove logic to recognise and delete no-op moves produced after forwarded uses (#167336)

As reported in <#166870>,
some copies with src==reg are not no-ops, e.g. when self-assigning a
w-reg on AArch64 which will zero-extend the corresponding x register.

Revert in order to fix the issue. We may revisit whether the
optimisation can be made safe at a later point.

Reverts dffbc03.
Fixes #166870.

Author: asb

llvm/lib/CodeGen/MachineCopyPropagation.cpp

@@ -937,16 +937,6 @@ void MachineCopyPropagation::ForwardCopyPropagateBlock(MachineBasicBlock &MBB) {
     if (CopyOperands) {
       Register RegSrc = CopyOperands->Source->getReg();
       Register RegDef = CopyOperands->Destination->getReg();
-      // It's possible that the previous transformations have resulted in a
-      // no-op register move (i.e. one where source and destination registers
-      // are the same and are not referring to a reserved register). If so,
-      // delete it.
-      if (RegSrc == RegDef && !MRI->isReserved(RegSrc)) {
-        MI.eraseFromParent();
-        NumDeletes++;
-        Changed = true;
-        continue;
-      }
 
       if (!TRI->regsOverlap(RegDef, RegSrc)) {
         // Copy is now a candidate for deletion.

llvm/test/CodeGen/AArch64/pr166870.ll

@@ -0,0 +1,68 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 6
+; RUN: llc -O3 < %s -mtriple=aarch64 | FileCheck %s
+
+; The seemingly redundant mov where src_reg == dst_reg shouldn't be removed,
+; because it has the effect of zeroing the upper bits in x8.
+
+define i32 @ham(i32 %arg, i1 %arg1, i1 %arg2, ptr %arg3) nounwind {
+; CHECK-LABEL: ham:
+; CHECK:       // %bb.0: // %bb
+; CHECK-NEXT:    stp x30, x21, [sp, #-32]! // 16-byte Folded Spill
+; CHECK-NEXT:    stp x20, x19, [sp, #16] // 16-byte Folded Spill
+; CHECK-NEXT:    tbnz w1, #0, .LBB0_3
+; CHECK-NEXT:  // %bb.1: // %bb4
+; CHECK-NEXT:    tbnz w2, #0, .LBB0_3
+; CHECK-NEXT:  // %bb.2: // %bb5
+; CHECK-NEXT:    mov x19, x3
+; CHECK-NEXT:    mov w21, w1
+; CHECK-NEXT:    mov w20, w0
+; CHECK-NEXT:    bl zot
+; CHECK-NEXT:    tbz w21, #0, .LBB0_4
+; CHECK-NEXT:  .LBB0_3: // %bb6
+; CHECK-NEXT:    ldp x20, x19, [sp, #16] // 16-byte Folded Reload
+; CHECK-NEXT:    mov w0, wzr
+; CHECK-NEXT:    ldp x30, x21, [sp], #32 // 16-byte Folded Reload
+; CHECK-NEXT:    ret
+; CHECK-NEXT:  .LBB0_4:
+; CHECK-NEXT:    mov w8, w20
+; CHECK-NEXT:    mov w20, wzr
+; CHECK-NEXT:    mov w8, w8
+; CHECK-NEXT:    mov w21, w8
+; CHECK-NEXT:  .LBB0_5: // %bb7
+; CHECK-NEXT:    // =>This Inner Loop Header: Depth=1
+; CHECK-NEXT:    strb w20, [x19]
+; CHECK-NEXT:    cbnz x21, .LBB0_5
+; CHECK-NEXT:  // %bb.6: // %bb8
+; CHECK-NEXT:    // in Loop: Header=BB0_5 Depth=1
+; CHECK-NEXT:    bl quux
+; CHECK-NEXT:    b .LBB0_5
+bb:
+  br i1 %arg1, label %bb6, label %bb4
+
+bb4:
+  %load = load ptr, ptr null, align 8
+  br i1 %arg2, label %bb6, label %bb5
+
+bb5:
+  %call = call i32 @zot() #0
+  %zext = zext i32 %arg to i64
+  br i1 %arg1, label %bb6, label %bb7
+
+bb6:
+  ret i32 0
+
+bb7:
+  store i8 0, ptr %arg3, align 1
+  %icmp = icmp eq i64 %zext, 0
+  br i1 %icmp, label %bb8, label %bb7
+
+bb8:
+  call void @quux()
+  br label %bb7
+}
+
+declare i32 @zot()
+
+declare void @quux()
+
+attributes #0 = { returns_twice }

llvm/test/CodeGen/RISCV/GlobalISel/constbarrier-rv32.ll

@@ -32,9 +32,12 @@ define void @constant_fold_barrier_i128(ptr %p) {
 ; RV32-NEXT:    mv a6, a1
 ; RV32-NEXT:    seqz a7, a1
 ; RV32-NEXT:    and a1, a7, a1
+; RV32-NEXT:    mv a1, a1
 ; RV32-NEXT:    mv a7, a1
 ; RV32-NEXT:    seqz a3, a1
 ; RV32-NEXT:    and a1, a3, a1
+; RV32-NEXT:    mv a1, a1
+; RV32-NEXT:    mv a1, a1
 ; RV32-NEXT:    sw a2, 0(a0)
 ; RV32-NEXT:    sw a6, 4(a0)
 ; RV32-NEXT:    sw a7, 8(a0)

llvm/test/CodeGen/RISCV/GlobalISel/div-by-constant.ll

@@ -103,15 +103,18 @@ define i64 @udiv64_constant_no_add(i64 %a) nounwind {
 ; RV32-NEXT:    mulhu a1, a1, a2
 ; RV32-NEXT:    add a5, a5, a6
 ; RV32-NEXT:    mv t0, t1
+; RV32-NEXT:    mv a1, a1
 ; RV32-NEXT:    sltu a4, a5, a6
 ; RV32-NEXT:    add a5, a5, a7
 ; RV32-NEXT:    sltu a6, t1, t1
 ; RV32-NEXT:    sltiu t1, t1, 0
 ; RV32-NEXT:    add t0, t0, t2
+; RV32-NEXT:    mv a1, a1
 ; RV32-NEXT:    sltu a2, a5, a7
 ; RV32-NEXT:    add a6, a6, t1
 ; RV32-NEXT:    sltu a5, t0, t2
 ; RV32-NEXT:    add t0, t0, a0
+; RV32-NEXT:    mv a1, a1
 ; RV32-NEXT:    add a2, a4, a2
 ; RV32-NEXT:    add a5, a6, a5
 ; RV32-NEXT:    sltu a0, t0, a0
@@ -155,6 +158,7 @@ define i64 @udiv64_constant_add(i64 %a) nounwind {
 ; RV32-NEXT:    mulhu a7, a0, a2
 ; RV32-NEXT:    mulhu t2, a1, a3
 ; RV32-NEXT:    mv t1, t2
+; RV32-NEXT:    mv t1, t1
 ; RV32-NEXT:    mul t2, a1, a3
 ; RV32-NEXT:    mulhu a2, a1, a2
 ; RV32-NEXT:    mulhu a3, a0, a3

llvm/test/CodeGen/RISCV/machine-copyprop-noop-removal.mir

@@ -1,8 +1,11 @@
 # NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 5
 # RUN: llc -o - %s -mtriple=riscv64 -run-pass=machine-cp -mcp-use-is-copy-instr | FileCheck %s
 
-## This test was added to capture a case where MachineCopyPropagation risks
-## leaving a no-op register move (add, x0, reg).
+## This test was added to capture a case where MachineCopyPropagation may
+## leave a no-op register move (add reg, x0, reg).
+## Due to the bug reported in
+## <https://github.com/llvm/llvm-project/issues/166870>, we are not currently
+## able to optimize this case.
 
 ---
 name: ham
@@ -21,6 +24,7 @@ body: |
   ; CHECK-NEXT:   liveins: $x10
   ; CHECK-NEXT: {{  $}}
   ; CHECK-NEXT:   $x11 = ADDI $x0, 0
+  ; CHECK-NEXT:   renamable $x10 = ADDI killed renamable $x10, 0
   ; CHECK-NEXT:   BEQ renamable $x10, $x0, %bb.4
   ; CHECK-NEXT: {{  $}}
   ; CHECK-NEXT: bb.2:

llvm/test/CodeGen/RISCV/sextw-removal.ll

@@ -1352,6 +1352,7 @@ define signext i32 @sextw_sh2add(i1 zeroext %0, ptr %1, i32 signext %2, i32 sign
 ; NOREMOVAL-LABEL: sextw_sh2add:
 ; NOREMOVAL:       # %bb.0:
 ; NOREMOVAL-NEXT:    sh2add a2, a2, a3
+; NOREMOVAL-NEXT:    mv a2, a2
 ; NOREMOVAL-NEXT:    beqz a0, .LBB22_2
 ; NOREMOVAL-NEXT:  # %bb.1:
 ; NOREMOVAL-NEXT:    sw a2, 0(a1)