@@ -2415,14 +2415,16 @@ multiclass INT_PTX_ATOM_CAS_AS<string atomic_cmp_swap_without_as, string type, s
24152415 !cast<PatFrag>(atomic_cmp_swap_without_as#_shared), !cast<Operand>("i"#type#"imm"), preds>;
24162416}
24172417
2418- // eg. with type = 32, order = .acquire, atomic_cmp_swap_pat = atomic_cmp_swap_i32_acquire, and _GEN becomes
2419- // F_ATOMIC_3<i32, Int32Regs, ".acquire", ".b32", ".cas", atomic_cmp_swap_i32_acquire, i32imm>
2418+ // eg. with type = 32, order = .acquire, addrspace = ".global",
2419+ // atomic_cmp_swap_pat = atomic_cmp_swap_i32_acquire_global.
2420+ // F_ATOMIC_3<i32, Int32Regs, ".acquire", ".global", ".b32",
2421+ // ".cas", atomic_cmp_swap_i32_acquire_global, i32imm>
24202422multiclass INT_PTX_ATOM_CAS<string atomic_cmp_swap_pat, string type,
2421- string order, string as , list<Predicate> preds>
2423+ string order, string addrspace , list<Predicate> preds>
24222424 : F_ATOMIC_3<!cast<ValueType>("i"#type),
24232425 !cast<NVPTXRegClass>("Int"#type#"Regs"),
24242426 order,
2425- as ,
2427+ addrspace ,
24262428 ".b"#type,
24272429 ".cas",
24282430 !cast<PatFrag>(atomic_cmp_swap_pat),
@@ -2431,20 +2433,20 @@ multiclass INT_PTX_ATOM_CAS<string atomic_cmp_swap_pat, string type,
24312433
24322434// Define atom.cas for all combinations of size x memory order supported in PTX *and* on the hardware.
24332435foreach size = ["32", "64"] in {
2434- foreach as = ["generic", "global", "shared"] in {
2435- defvar cas_as_string = !if(!eq(as , "generic"), "", "."#as );
2436+ foreach addrspace = ["generic", "global", "shared"] in {
2437+ defvar cas_addrspace_string = !if(!eq(addrspace , "generic"), "", "."#addrspace );
24362438 foreach order = ["acquire", "release", "acq_rel", "monotonic"] in {
2437- defvar order_as_string = !if(!eq(order, "monotonic"), ".relaxed", "."#order);
2439+ defvar cas_order_string = !if(!eq(order, "monotonic"), ".relaxed", "."#order);
24382440 // Note that AtomicExpand will convert cmpxchg seq_cst to a cmpxchg monotonic with fences around it.
24392441 // Memory orders are only supported for SM70+, PTX63+- so we have two sets of instruction definitions-
24402442 // for SM70+, and "old" ones which lower to "atom.cas", for earlier archs.
2441- defm INT_PTX_ATOM_CAS_#size#_#order#as
2442- : INT_PTX_ATOM_CAS<"atomic_cmp_swap_i"#size#_#order#_#as , size,
2443- order_as_string, cas_as_string ,
2443+ defm INT_PTX_ATOM_CAS_#size#_#order#addrspace
2444+ : INT_PTX_ATOM_CAS<"atomic_cmp_swap_i"#size#_#order#_#addrspace , size,
2445+ cas_order_string, cas_addrspace_string ,
24442446 [hasSM<70>, hasPTX<63>]>;
2445- defm INT_PTX_ATOM_CAS_#size#_#order#_old#as
2446- : INT_PTX_ATOM_CAS<"atomic_cmp_swap_i"#size#_#order#_#as , size,
2447- "", cas_as_string , []>;
2447+ defm INT_PTX_ATOM_CAS_#size#_#order#_old#addrspace
2448+ : INT_PTX_ATOM_CAS<"atomic_cmp_swap_i"#size#_#order#_#addrspace , size,
2449+ "", cas_addrspace_string , []>;
24482450 }
24492451 }
24502452}
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