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| 1 | +//===-- RISCVInstrInfoP.td - RISC-V 'P' instructions -------*- tablegen -*-===// |
| 2 | +// |
| 3 | +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. |
| 4 | +// See https://llvm.org/LICENSE.txt for license information. |
| 5 | +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception |
| 6 | +// |
| 7 | +//===----------------------------------------------------------------------===// |
| 8 | +// |
| 9 | +// This file describes the RISC-V instructions from the standard 'Base P' |
| 10 | +// Packed SIMD instruction set extension. |
| 11 | +// |
| 12 | +// This version is still experimental as the 'P' extension hasn't been |
| 13 | +// ratified yet. |
| 14 | +// |
| 15 | +//===----------------------------------------------------------------------===// |
| 16 | + |
| 17 | +//===----------------------------------------------------------------------===// |
| 18 | +// Operand and SDNode transformation definitions. |
| 19 | +//===----------------------------------------------------------------------===// |
| 20 | + |
| 21 | +def RVPGPRPairRV32 : RegisterOperand<GPRPair> { |
| 22 | + let ParserMatchClass = GPRPairRV32Operand; |
| 23 | + let EncoderMethod = "getRVPGPRPair"; |
| 24 | + let DecoderMethod = "decodeRVPGPRPair"; |
| 25 | +} |
| 26 | + |
| 27 | +def simm10 : RISCVSImmLeafOp<10>; |
| 28 | + |
| 29 | +//===----------------------------------------------------------------------===// |
| 30 | +// Instruction class templates |
| 31 | +//===----------------------------------------------------------------------===// |
| 32 | + |
| 33 | +let hasSideEffects = 0, mayLoad = 0, mayStore = 0 in |
| 34 | +class RVPUnaryImm9<bits<7> funct7, string opcodestr> |
| 35 | + : RVInstIBase<0b010, OPC_OP_IMM_32, (outs GPR:$rd), (ins simm10:$simm10), |
| 36 | + opcodestr, "$rd, $simm10"> { |
| 37 | + bits<10> simm10; |
| 38 | + |
| 39 | + let Inst{31-25} = funct7; |
| 40 | + let Inst{24-15} = simm10; |
| 41 | +} |
| 42 | + |
| 43 | +let hasSideEffects = 0, mayLoad = 0, mayStore = 0 in |
| 44 | +class RVPUnaryImm9Rdp<bits<7> funct7, string opcodestr> |
| 45 | + : RVInstIBase<0b010, OPC_OP_IMM_32, (outs RVPGPRPairRV32:$rdp), |
| 46 | + (ins simm10:$simm10), |
| 47 | + opcodestr, "$rdp, $simm10"> { |
| 48 | + bits<10> simm10; |
| 49 | + bits<4> rdp; |
| 50 | + |
| 51 | + let Inst{31-25} = funct7; |
| 52 | + let Inst{24-15} = simm10; |
| 53 | + let Inst{11-8} = rdp; |
| 54 | + let Inst{7} = 0b0; |
| 55 | +} |
| 56 | + |
| 57 | +let hasSideEffects = 0, mayLoad = 0, mayStore = 0 in |
| 58 | +class RVPUnaryImm8<bits<8> funct8, string opcodestr> |
| 59 | + : RVInstIBase<0b010, OPC_OP_IMM_32, (outs GPR:$rd), (ins uimm8:$uimm8), |
| 60 | + opcodestr, "$rd, $uimm8"> { |
| 61 | + bits<8> uimm8; |
| 62 | + |
| 63 | + let Inst{31-24} = funct8; |
| 64 | + let Inst{23-16} = uimm8; |
| 65 | + let Inst{15} = 0b0; |
| 66 | +} |
| 67 | + |
| 68 | +let hasSideEffects = 0, mayLoad = 0, mayStore = 0 in |
| 69 | +class RVPUnaryImm5<bits<3> f, string opcodestr> |
| 70 | + : RVInstIBase<0b010, OPC_OP_IMM_32, (outs GPR:$rd), |
| 71 | + (ins GPR:$rs1, uimm5:$uimm5), opcodestr, "$rd, $rs1, $uimm5"> { |
| 72 | + bits<5> uimm5; |
| 73 | + let Inst{31} = 0b1; |
| 74 | + let Inst{30-28} = f; |
| 75 | + let Inst{27} = 0b0; |
| 76 | + let Inst{26-25} = 0b01; |
| 77 | + let Inst{24-20} = uimm5; |
| 78 | +} |
| 79 | + |
| 80 | +let hasSideEffects = 0, mayLoad = 0, mayStore = 0 in |
| 81 | +class RVPUnaryImm4<bits<3> f, string opcodestr> |
| 82 | + : RVInstIBase<0b010, OPC_OP_IMM_32, (outs GPR:$rd), |
| 83 | + (ins GPR:$rs1, uimm4:$uimm4), opcodestr, "$rd, $rs1, $uimm4"> { |
| 84 | + bits<4> uimm4; |
| 85 | + let Inst{31} = 0b1; |
| 86 | + let Inst{30-28} = f; |
| 87 | + let Inst{27} = 0b0; |
| 88 | + let Inst{26-24} = 0b001; |
| 89 | + let Inst{23-20} = uimm4; |
| 90 | +} |
| 91 | + |
| 92 | +let hasSideEffects = 0, mayLoad = 0, mayStore = 0 in |
| 93 | +class RVPUnaryImm3<bits<3> f, string opcodestr> |
| 94 | + : RVInstIBase<0b010, OPC_OP_IMM_32, (outs GPR:$rd), |
| 95 | + (ins GPR:$rs1, uimm3:$uimm3), opcodestr, "$rd, $rs1, $uimm3"> { |
| 96 | + bits<3> uimm3; |
| 97 | + let Inst{31} = 0b1; |
| 98 | + let Inst{30-28} = f; |
| 99 | + let Inst{27} = 0b0; |
| 100 | + let Inst{26-23} = 0b0001; |
| 101 | + let Inst{22-20} = uimm3; |
| 102 | +} |
| 103 | + |
| 104 | +let hasSideEffects = 0, mayLoad = 0, mayStore = 0 in |
| 105 | +class RVPUnaryWUF<bits<2> w, bits<5> uf, string opcodestr> |
| 106 | + : RVInstIBase<0b010, OPC_OP_IMM_32, (outs GPR:$rd), (ins GPR:$rs1), |
| 107 | + opcodestr, "$rd, $rs1"> { |
| 108 | + let Inst{31-27} = 0b11100; |
| 109 | + let Inst{26-25} = w; |
| 110 | + let Inst{24-20} = uf; |
| 111 | +} |
| 112 | + |
| 113 | +//===----------------------------------------------------------------------===// |
| 114 | +// Instructions |
| 115 | +//===----------------------------------------------------------------------===// |
| 116 | + |
| 117 | +let Predicates = [HasStdExtP] in { |
| 118 | +def CLS : Unary_r<0b011000000011, 0b001, "cls">; |
| 119 | +def ABS : Unary_r<0b011000000111, 0b001, "abs">; |
| 120 | +} // Predicates = [HasStdExtP] |
| 121 | +let Predicates = [HasStdExtP, IsRV32] in |
| 122 | +def REV_RV32 : Unary_r<0b011010011111, 0b101, "rev">; |
| 123 | + |
| 124 | +let Predicates = [HasStdExtP, IsRV64] in { |
| 125 | +def REV16 : Unary_r<0b011010110000, 0b101, "rev16">; |
| 126 | +def REV_RV64 : Unary_r<0b011110111111, 0b101, "rev">; |
| 127 | + |
| 128 | +def CLSW : UnaryW_r<0b011000000011, 0b001, "clsw">; |
| 129 | +def ABSW : UnaryW_r<0b011000000111, 0b001, "absw">; |
| 130 | +} // Predicates = [HasStdExtP, IsRV64] |
| 131 | + |
| 132 | +let Predicates = [HasStdExtP] in { |
| 133 | +def PSLLI_B : RVPUnaryImm3<0b000, "pslli.b">; |
| 134 | +def PSLLI_H : RVPUnaryImm4<0b000, "pslli.h">; |
| 135 | +def PSSLAI_H : RVPUnaryImm4<0b101, "psslai.h">; |
| 136 | +} // Predicates = [HasStdExtP] |
| 137 | +let DecoderNamespace = "RV32Only", |
| 138 | + Predicates = [HasStdExtP, IsRV32] in |
| 139 | +def SSLAI : RVPUnaryImm5<0b101, "sslai">; |
| 140 | +let Predicates = [HasStdExtP, IsRV64] in { |
| 141 | +def PSLLI_W : RVPUnaryImm5<0b000, "pslli.w">; |
| 142 | +def PSSLAI_W : RVPUnaryImm5<0b101, "psslai.w">; |
| 143 | +} // Predicates = [HasStdExtP, IsRV64] |
| 144 | + |
| 145 | +let Predicates = [HasStdExtP] in |
| 146 | +def PLI_H : RVPUnaryImm9<0b1011000, "pli.h">; |
| 147 | +let Predicates = [HasStdExtP, IsRV64] in |
| 148 | +def PLI_W : RVPUnaryImm9<0b1011001, "pli.w">; |
| 149 | +let Predicates = [HasStdExtP] in |
| 150 | +def PLI_B : RVPUnaryImm8<0b10110100, "pli.b">; |
| 151 | + |
| 152 | +let Predicates = [HasStdExtP] in { |
| 153 | +def PSEXT_H_B : RVPUnaryWUF<0b00, 0b00100, "psext.h.b">; |
| 154 | +def PSABS_H : RVPUnaryWUF<0b00, 0b00111, "psabs.h">; |
| 155 | +def PSABS_B : RVPUnaryWUF<0b10, 0b00111, "psabs.b">; |
| 156 | +} // Predicates = [HasStdExtP] |
| 157 | +let Predicates = [HasStdExtP, IsRV64] in { |
| 158 | +def PSEXT_W_B : RVPUnaryWUF<0b01, 0b00100, "psext.w.b">; |
| 159 | +def PSEXT_W_H : RVPUnaryWUF<0b01, 0b00101, "psext.w.h">; |
| 160 | +} // Predicates = [HasStdExtP, IsRV64] |
| 161 | + |
| 162 | +let Predicates = [HasStdExtP] in |
| 163 | +def PLUI_H : RVPUnaryImm9<0b1111000, "plui.h">; |
| 164 | +let Predicates = [HasStdExtP, IsRV64] in |
| 165 | +def PLUI_W : RVPUnaryImm9<0b1111001, "plui.w">; |
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