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tgymnichtgymnich
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add draft for InferTypeInfoPass
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‎llvm/include/llvm/CodeGen/GlobalISel/InferTypeInfoPass.h‎

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#ifndef LLVM_CODEGEN_GLOBALISEL_INFERTYPEINFOPASS_H
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#define LLVM_CODEGEN_GLOBALISEL_INFERTYPEINFOPASS_H
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#include "llvm/Analysis/AliasAnalysis.h"
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#include "llvm/CodeGen/GlobalISel/MachineIRBuilder.h"
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#include "llvm/CodeGen/MachineFunction.h"
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#include "llvm/CodeGen/MachineFunctionPass.h"
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namespace llvm {
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class InferTypeInfo : public MachineFunctionPass {
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public:
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static char ID;
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private:
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MachineRegisterInfo *MRI = nullptr;
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MachineFunction *MF = nullptr;
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MachineIRBuilder Builder;
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/// Initialize the field members using \p MF.
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void init(MachineFunction &MF);
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public:
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InferTypeInfo() : MachineFunctionPass(ID) {}
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void getAnalysisUsage(AnalysisUsage &AU) const override;
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bool runOnMachineFunction(MachineFunction &MF) override;
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private:
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bool inferTypeInfo(MachineFunction &MF);
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bool shouldBeFP(MachineOperand &Op, unsigned Depth) const;
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void updateDef(Register Reg);
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void updateUse(MachineOperand &Op, bool FP);
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};
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} // end namespace llvm
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#endif // LLVM_CODEGEN_GLOBALISEL_INFERTYPEINFOPASS_H

‎llvm/include/llvm/InitializePasses.h‎

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@@ -131,6 +131,7 @@ void initializeHardwareLoopsLegacyPass(PassRegistry &);
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void initializeMIRProfileLoaderPassPass(PassRegistry &);
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void initializeIRSimilarityIdentifierWrapperPassPass(PassRegistry &);
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void initializeIRTranslatorPass(PassRegistry &);
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void initializeInferTypeInfoPass(PassRegistry &);
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void initializeIVUsersWrapperPassPass(PassRegistry &);
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void initializeIfConverterPass(PassRegistry &);
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void initializeImmutableModuleSummaryIndexWrapperPassPass(PassRegistry &);

‎llvm/lib/CodeGen/GlobalISel/CMakeLists.txt‎

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@@ -13,6 +13,7 @@ add_llvm_component_library(LLVMGlobalISel
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GIMatchTableExecutor.cpp
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GISelChangeObserver.cpp
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IRTranslator.cpp
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InferTypeInfoPass.cpp
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InlineAsmLowering.cpp
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InstructionSelect.cpp
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InstructionSelector.cpp

‎llvm/lib/CodeGen/GlobalISel/GlobalISel.cpp‎

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@@ -16,6 +16,7 @@ using namespace llvm;
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void llvm::initializeGlobalISel(PassRegistry &Registry) {
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initializeIRTranslatorPass(Registry);
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initializeInferTypeInfoPass(Registry);
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initializeLegalizerPass(Registry);
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initializeLoadStoreOptPass(Registry);
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initializeLocalizerPass(Registry);

‎llvm/lib/CodeGen/GlobalISel/InferTypeInfoPass.cpp‎

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//===- llvm/CodeGen/GlobalISel/InferTypeInfoPass.cpp - StripTypeInfoPass ---*-
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// C++ -*-==//
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//
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// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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// See https://llvm.org/LICENSE.txt for license information.
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// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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//
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//===----------------------------------------------------------------------===//
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/// \file
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/// This file implements the InferTypeInfoPass class.
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//===----------------------------------------------------------------------===//
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#include "llvm/CodeGen/GlobalISel/InferTypeInfoPass.h"
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#include "llvm/ADT/STLExtras.h"
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#include "llvm/ADT/SmallSet.h"
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#include "llvm/Analysis/AliasAnalysis.h"
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#include "llvm/CodeGen/GlobalISel/GenericMachineInstrs.h"
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#include "llvm/CodeGen/GlobalISel/LegalizerInfo.h"
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#include "llvm/CodeGen/GlobalISel/LoadStoreOpt.h"
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#include "llvm/CodeGen/GlobalISel/Utils.h"
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#include "llvm/CodeGen/MachineBasicBlock.h"
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#include "llvm/CodeGen/MachineFrameInfo.h"
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#include "llvm/CodeGen/MachineFunction.h"
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#include "llvm/CodeGen/MachineInstr.h"
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#include "llvm/CodeGen/MachineMemOperand.h"
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#include "llvm/CodeGen/MachineOperand.h"
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#include "llvm/CodeGen/MachineOptimizationRemarkEmitter.h"
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#include "llvm/CodeGen/MachineRegisterInfo.h"
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#include "llvm/CodeGen/Register.h"
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#include "llvm/CodeGen/TargetLowering.h"
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#include "llvm/CodeGen/TargetOpcodes.h"
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#include "llvm/IR/IntrinsicInst.h"
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#include "llvm/IR/IntrinsicsAMDGPU.h"
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#include "llvm/InitializePasses.h"
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#define DEBUG_TYPE "mir-infer-type-info"
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using namespace llvm;
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char InferTypeInfo::ID = 0;
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INITIALIZE_PASS_BEGIN(InferTypeInfo, DEBUG_TYPE, "TODO", false, false)
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INITIALIZE_PASS_END(InferTypeInfo, DEBUG_TYPE, "TODO", false, false)
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void InferTypeInfo::init(MachineFunction &MF) {
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this->MF = &MF;
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MRI = &MF.getRegInfo();
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Builder.setMF(MF);
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}
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void InferTypeInfo::getAnalysisUsage(AnalysisUsage &AU) const {
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AU.setPreservesAll();
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MachineFunctionPass::getAnalysisUsage(AU);
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}
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static LLT updateType(LLT Ty, bool FP) {
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LLT InferredScalarTy =
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FP ? LLT::floatingPoint(Ty.getScalarSizeInBits(), LLT::FPInfo::IEEE_FLOAT)
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: LLT::integer(Ty.getScalarSizeInBits());
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LLT InferredTy =
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Ty.isVector() ? Ty.changeElementType(InferredScalarTy) : InferredScalarTy;
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return InferredTy;
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}
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void InferTypeInfo::updateDef(Register Reg) {
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LLT Ty = MRI->getType(Reg);
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LLT InferredTy = updateType(Ty, false);
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MRI->setType(Reg, InferredTy);
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}
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void InferTypeInfo::updateUse(MachineOperand &Op, bool FP) {
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assert(Op.isReg());
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LLT Ty = MRI->getType(Op.getReg());
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LLT InferredTy = updateType(Ty, FP);
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MachineOperand *Def = MRI->getOneDef(Op.getReg());
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MachineInstr *MI = Op.getParent();
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MachineBasicBlock *MBB = MI->getParent();
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Builder.setInsertPt(*MBB, MI);
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auto Bitcast = Builder.buildBitcast(InferredTy, Def->getReg());
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Op.setReg(Bitcast.getReg(0));
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}
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constexpr unsigned MaxFPRSearchDepth = 5;
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bool InferTypeInfo::shouldBeFP(MachineOperand &Op, unsigned Depth = 0) const {
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if (Depth > MaxFPRSearchDepth)
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return false;
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if (!Op.isReg())
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return false;
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MachineInstr &MI = *Op.getParent();
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auto Pred = [&](MachineOperand &O) { return shouldBeFP(O, Depth + 1); };
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// TODO: cache FP registers
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switch (MI.getOpcode()) {
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// def and use fp instructions
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case TargetOpcode::G_FABS:
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case TargetOpcode::G_FADD:
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case TargetOpcode::G_FCANONICALIZE:
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case TargetOpcode::G_FCEIL:
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case TargetOpcode::G_FCONSTANT:
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case TargetOpcode::G_FCOPYSIGN:
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case TargetOpcode::G_FCOS:
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case TargetOpcode::G_FDIV:
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case TargetOpcode::G_FEXP2:
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case TargetOpcode::G_FEXP:
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case TargetOpcode::G_FFLOOR:
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case TargetOpcode::G_FLOG10:
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case TargetOpcode::G_FLOG2:
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case TargetOpcode::G_FLOG:
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case TargetOpcode::G_FMA:
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case TargetOpcode::G_FMAD:
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case TargetOpcode::G_FMAXIMUM:
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case TargetOpcode::G_FMAXNUM:
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case TargetOpcode::G_FMAXNUM_IEEE:
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case TargetOpcode::G_FMINIMUM:
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case TargetOpcode::G_FMINNUM:
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case TargetOpcode::G_FMINNUM_IEEE:
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case TargetOpcode::G_FMUL:
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case TargetOpcode::G_FNEARBYINT:
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case TargetOpcode::G_FNEG:
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case TargetOpcode::G_FPEXT:
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case TargetOpcode::G_FPOW:
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case TargetOpcode::G_FPTRUNC:
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case TargetOpcode::G_FREM:
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case TargetOpcode::G_FRINT:
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case TargetOpcode::G_FSIN:
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case TargetOpcode::G_FTAN:
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case TargetOpcode::G_FACOS:
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case TargetOpcode::G_FASIN:
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case TargetOpcode::G_FATAN:
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case TargetOpcode::G_FATAN2:
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case TargetOpcode::G_FCOSH:
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case TargetOpcode::G_FSINH:
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case TargetOpcode::G_FTANH:
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case TargetOpcode::G_FSQRT:
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case TargetOpcode::G_FSUB:
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case TargetOpcode::G_INTRINSIC_ROUND:
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case TargetOpcode::G_INTRINSIC_ROUNDEVEN:
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case TargetOpcode::G_INTRINSIC_TRUNC:
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case TargetOpcode::G_VECREDUCE_FADD:
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case TargetOpcode::G_VECREDUCE_FMUL:
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case TargetOpcode::G_VECREDUCE_FMAX:
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case TargetOpcode::G_VECREDUCE_FMIN:
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case TargetOpcode::G_VECREDUCE_FMAXIMUM:
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case TargetOpcode::G_VECREDUCE_FMINIMUM:
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case TargetOpcode::G_VECREDUCE_SEQ_FADD:
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case TargetOpcode::G_VECREDUCE_SEQ_FMUL:
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return true;
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// use only fp instructions
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case TargetOpcode::G_SITOFP:
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case TargetOpcode::G_UITOFP:
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return Op.isDef();
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// def only fp instructions
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case TargetOpcode::G_FPTOSI:
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case TargetOpcode::G_FPTOUI:
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case TargetOpcode::G_FPTOSI_SAT:
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case TargetOpcode::G_FPTOUI_SAT:
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case TargetOpcode::G_FCMP:
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case TargetOpcode::G_LROUND:
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case TargetOpcode::G_LLROUND:
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return Op.isUse();
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case TargetOpcode::G_FREEZE:
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case TargetOpcode::G_IMPLICIT_DEF:
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case TargetOpcode::G_PHI:
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case TargetOpcode::G_SELECT:
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case TargetOpcode::G_BUILD_VECTOR:
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case TargetOpcode::G_CONCAT_VECTORS:
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case TargetOpcode::G_INSERT_SUBVECTOR:
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case TargetOpcode::G_EXTRACT_SUBVECTOR:
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case TargetOpcode::G_SHUFFLE_VECTOR:
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case TargetOpcode::G_SPLAT_VECTOR:
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case TargetOpcode::G_STEP_VECTOR:
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case TargetOpcode::G_VECTOR_COMPRESS: {
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return all_of(MI.all_defs(),
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[&](MachineOperand &O) {
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return all_of(MRI->use_operands(O.getReg()), Pred);
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}) &&
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all_of(MI.all_uses(), [&](MachineOperand &O) {
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return all_of(MRI->def_operands(O.getReg()), Pred);
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});
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}
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case TargetOpcode::G_INSERT_VECTOR_ELT:
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case TargetOpcode::G_EXTRACT_VECTOR_ELT: {
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MachineOperand &Dst = MI.getOperand(0);
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MachineOperand &LHS = MI.getOperand(1);
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MachineOperand &RHS = MI.getOperand(2);
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return all_of(MRI->use_operands(Dst.getReg()), Pred) &&
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(!LHS.isReg() || all_of(MRI->def_operands(LHS.getReg()), Pred)) &&
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(!RHS.isReg() || all_of(MRI->def_operands(RHS.getReg()), Pred));
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}
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case TargetOpcode::G_STORE:
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case TargetOpcode::G_INDEXED_STORE: {
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MachineOperand &Val = MI.getOperand(0);
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return Op.getReg() == Val.getReg() && all_of(MRI->def_operands(Op.getReg()), Pred);
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}
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case TargetOpcode::G_INDEXED_LOAD:
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case TargetOpcode::G_LOAD: {
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MachineOperand &Dst = MI.getOperand(0);
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return Op.getReg() == Dst.getReg() && all_of(MRI->use_operands(Dst.getReg()), Pred);
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}
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case TargetOpcode::G_ATOMICRMW_FADD:
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case TargetOpcode::G_ATOMICRMW_FSUB:
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case TargetOpcode::G_ATOMICRMW_FMAX:
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case TargetOpcode::G_ATOMICRMW_FMIN: {
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MachineOperand &WriteBack = MI.getOperand(0);
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MachineOperand &FPOp = MI.getOperand(2);
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return Op.getReg() == WriteBack.getReg() || Op.getReg() == FPOp.getReg();
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}
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case TargetOpcode::G_INTRINSIC_CONVERGENT:
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case TargetOpcode::G_INTRINSIC_CONVERGENT_W_SIDE_EFFECTS:
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case TargetOpcode::G_INTRINSIC_W_SIDE_EFFECTS:
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case TargetOpcode::G_INTRINSIC: {
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GIntrinsic *Intrinsic = dyn_cast<GIntrinsic>(&MI);
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if (!Intrinsic)
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return false;
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switch (Intrinsic->getIntrinsicID()) {
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case Intrinsic::amdgcn_rcp:
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case Intrinsic::amdgcn_log:
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case Intrinsic::amdgcn_exp2:
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case Intrinsic::amdgcn_rsq:
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case Intrinsic::amdgcn_sqrt:
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case Intrinsic::amdgcn_fdot2_f16_f16:
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case Intrinsic::amdgcn_mfma_f32_4x4x4f16:
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return true;
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default:
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return false;
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}
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return false;
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}
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default:
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break;
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}
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return false;
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}
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bool InferTypeInfo::inferTypeInfo(MachineFunction &MF) {
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bool Changed = false;
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for (MachineBasicBlock &MBB : MF) {
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for (MachineInstr &MI : MBB.instrs()) {
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for (auto &Def : MI.all_defs()) {
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if (shouldBeFP(Def)) {
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updateDef(Def.getReg());
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Changed |= true;
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}
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}
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for (auto &Use : MI.all_uses()) {
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bool IsFPDef =
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MRI->getVRegDef(Use.getReg()) &&
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all_of(MRI->def_operands(Use.getReg()),
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[&](MachineOperand &Op) { return shouldBeFP(Op); });
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bool IsFPUse = shouldBeFP(Use);
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if (IsFPUse && !IsFPDef) {
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updateUse(Use, true);
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Changed |= true;
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} else if (!IsFPUse && IsFPDef) {
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updateUse(Use, false);
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Changed |= true;
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}
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}
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for (auto &MemOp: MI.memoperands()) {
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bool IsFP = any_of(MI.all_defs(), [&](MachineOperand &O){ return shouldBeFP(O); }) ||
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any_of(MI.all_uses(), [&](MachineOperand &O){ return shouldBeFP(O); });
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if (!IsFP)
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continue;
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LLT Ty = MemOp->getType();
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LLT NewTy = updateType(Ty, true);
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MemOp->setType(NewTy);
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}
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}
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}
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return Changed;
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}
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bool InferTypeInfo::runOnMachineFunction(MachineFunction &MF) {
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init(MF);
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bool Changed = false;
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Changed |= inferTypeInfo(MF);
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return Changed;
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}

‎llvm/utils/gn/secondary/llvm/lib/CodeGen/GlobalISel/BUILD.gn‎

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@@ -26,6 +26,7 @@ static_library("GlobalISel") {
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"GISelKnownBits.cpp",
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"GlobalISel.cpp",
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"IRTranslator.cpp",
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"InferTypeInfoPass.cpp",
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"InlineAsmLowering.cpp",
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"InstructionSelect.cpp",
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"InstructionSelector.cpp",

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