[LV] Check debug location for more recipes in vplan-printing.ll.

Extend test to check printing of debug locations to cover a range of
wide and replicating recipes. Currently those do not print the debug
metadata.

Author: fhahn

llvm/test/Transforms/LoopVectorize/vplan-printing.ll

@@ -329,8 +329,8 @@ for.end:
   ret void
 }
 
-define void @debug_loc_vpinstruction(ptr nocapture %asd, ptr nocapture %bsd) !dbg !5 {
-; CHECK-LABEL: Checking a loop in 'debug_loc_vpinstruction'
+define void @recipe_debug_loc_location(ptr nocapture %src) !dbg !5 {
+; CHECK-LABEL: Checking a loop in 'recipe_debug_loc_location'
 ; CHECK:    VPlan 'Initial VPlan for VF={4},UF>=1' {
 ; CHECK-NEXT: Live-in vp<[[VF:%.]]> = VF
 ; CHECK-NEXT: Live-in vp<[[VFxUF:%.]]> = VF * UF
@@ -347,14 +347,20 @@ define void @debug_loc_vpinstruction(ptr nocapture %asd, ptr nocapture %bsd) !db
 ; CHECK-NEXT:  vector.body:
 ; CHECK-NEXT:    EMIT vp<[[CAN_IV:%.+]]> = CANONICAL-INDUCTION ir<0>, vp<[[CAN_IV_NEXT:%.+]]>
 ; CHECK-NEXT:    vp<[[STEPS:%.+]]> = SCALAR-STEPS vp<[[CAN_IV]]>, ir<1>, vp<[[VF]]>
-; CHECK-NEXT:    CLONE ir<%isd> = getelementptr inbounds ir<%asd>, vp<[[STEPS]]>
+; CHECK-NEXT:    CLONE ir<%isd> = getelementptr inbounds ir<%src>, vp<[[STEPS]]>
+; CHECK-NOT:     !dbg
 ; CHECK-NEXT:    vp<[[VEC_PTR:%.+]]> = vector-pointer ir<%isd>
+; CHECK-NOT:     !dbg
 ; CHECK-NEXT:    WIDEN ir<%lsd> = load vp<[[VEC_PTR]]>
+; CHECK-NOT:     !dbg
 ; CHECK-NEXT:    WIDEN ir<%psd> = add nuw nsw ir<%lsd>, ir<23>
+; CHECK-NOT:     !dbg
 ; CHECK-NEXT:    WIDEN ir<%cmp1> = icmp slt ir<%lsd>, ir<100>
-; CHECK-NEXT:    EMIT vp<[[NOT1:%.+]]> = not ir<%cmp1>, !dbg /tmp/s.c:5:3
+; CHECK-NOT:     !dbg
+; CHECK-NEXT:    EMIT vp<[[NOT1:%.+]]> = not ir<%cmp1>, !dbg /tmp/s.c:9:3
 ; CHECK-NEXT:    WIDEN ir<%cmp2> = icmp sge ir<%lsd>, ir<200>
-; CHECK-NEXT:    EMIT vp<[[SEL1:%.+]]> = logical-and vp<[[NOT1]]>, ir<%cmp2>, !dbg /tmp/s.c:5:21
+; CHECK-NOT:     !dbg
+; CHECK-NEXT:    EMIT vp<[[SEL1:%.+]]> = logical-and vp<[[NOT1]]>, ir<%cmp2>, !dbg /tmp/s.c:11:3
 ; CHECK-NEXT:    EMIT vp<[[OR1:%.+]]> = or vp<[[SEL1]]>, ir<%cmp1>
 ; CHECK-NEXT:  Successor(s): pred.sdiv
 ; CHECK-EMPTY:
@@ -365,18 +371,23 @@ define void @debug_loc_vpinstruction(ptr nocapture %asd, ptr nocapture %bsd) !db
 ; CHECK-EMPTY:
 ; CHECK-NEXT:    pred.sdiv.if:
 ; CHECK-NEXT:      REPLICATE ir<%sd1> = sdiv ir<%psd>, ir<%lsd> (S->V)
+; CHECK-NOT:       !dbg
 ; CHECK-NEXT:    Successor(s): pred.sdiv.continue
 ; CHECK-EMPTY:
 ; CHECK-NEXT:    pred.sdiv.continue:
 ; CHECK-NEXT:      PHI-PREDICATED-INSTRUCTION vp<[[PHI:%.+]]> = ir<%sd1>
+; CHECK-NOT:       !dbg
 ; CHECK-NEXT:    No successors
 ; CHECK-NEXT:  }
 ; CHECK-NEXT:  Successor(s): if.then.0
 ; CHECK-EMPTY:
 ; CHECK-NEXT:  if.then.0:
 ; CHECK-NEXT:    BLEND ir<%ysd.0> = ir<%psd> vp<[[PHI]]>/vp<[[OR1]]>
+; CHECK-NOT:     !dbg
 ; CHECK-NEXT:    vp<[[VEC_PTR2:%.+]]> = vector-pointer ir<%isd>
+; CHECK-NOT:     !dbg
 ; CHECK-NEXT:    WIDEN store vp<[[VEC_PTR2]]>, ir<%ysd.0>
+; CHECK-NOT:     !dbg
 ; CHECK-NEXT:    EMIT vp<[[CAN_IV_NEXT]]> = add nuw vp<[[CAN_IV]]>, vp<[[VFxUF]]>
 ; CHECK-NEXT:    EMIT branch-on-count vp<[[CAN_IV_NEXT]]>, vp<[[VTC]]>
 ; CHECK-NEXT:  No successors
@@ -406,23 +417,23 @@ entry:
 
 loop:
   %iv = phi i64 [ 0, %entry ], [ %iv.next, %if.end ]
-  %isd = getelementptr inbounds i32, ptr %asd, i64 %iv
-  %lsd = load i32, ptr %isd, align 4
-  %psd = add nuw nsw i32 %lsd, 23
-  %cmp1 = icmp slt i32 %lsd, 100
-  br i1 %cmp1, label %if.then, label %check, !dbg !7
+  %isd = getelementptr inbounds i32, ptr %src, i64 %iv, !dbg !7
+  %lsd = load i32, ptr %isd, align 4, !dbg !8
+  %psd = add nuw nsw i32 %lsd, 23, !dbg !9
+  %cmp1 = icmp slt i32 %lsd, 100, !dbg !10
+  br i1 %cmp1, label %if.then, label %check, !dbg !11
 
 check:
-  %cmp2 = icmp sge i32 %lsd, 200
-  br i1 %cmp2, label %if.then, label %if.end, !dbg !8
+  %cmp2 = icmp sge i32 %lsd, 200, !dbg !12
+  br i1 %cmp2, label %if.then, label %if.end, !dbg !13
 
 if.then:
-  %sd1 = sdiv i32 %psd, %lsd
+  %sd1 = sdiv i32 %psd, %lsd, !dbg !14
   br label %if.end
 
 if.end:
-  %ysd.0 = phi i32 [ %sd1, %if.then ], [ %psd, %check ]
-  store i32 %ysd.0, ptr %isd, align 4
+  %ysd.0 = phi i32 [ %sd1, %if.then ], [ %psd, %check ], !dbg !16
+  store i32 %ysd.0, ptr %isd, align 4, !dbg !17
   %iv.next = add nuw nsw i64 %iv, 1
   %exitcond = icmp eq i64 %iv.next, 128
   br i1 %exitcond, label %exit, label %loop
@@ -1078,4 +1089,15 @@ attributes #0 = { readonly nounwind "vector-function-abi-variant"="_ZGV_LLVM_M2v
 !5 = distinct !DISubprogram(name: "f", scope: !1, file: !1, line: 4, type: !6, scopeLine: 4, flags: DIFlagPrototyped, spFlags: DISPFlagDefinition | DISPFlagOptimized, unit: !0, retainedNodes: !2)
 !6 = !DISubroutineType(types: !2)
 !7 = !DILocation(line: 5, column: 3, scope: !5)
-!8 = !DILocation(line: 5, column: 21, scope: !5)
+!8 = !DILocation(line: 6, column: 3, scope: !5)
+!9 = !DILocation(line: 7, column: 3, scope: !5)
+!10 = !DILocation(line: 8, column: 3, scope: !5)
+!11 = !DILocation(line: 9, column: 3, scope: !5)
+!12 = !DILocation(line: 10, column: 3, scope: !5)
+!13 = !DILocation(line: 11, column: 3, scope: !5)
+!14 = !DILocation(line: 12, column: 3, scope: !5)
+!15 = !DILocation(line: 13, column: 3, scope: !5)
+!16 = !DILocation(line: 14, column: 3, scope: !5)
+!17 = !DILocation(line: 15, column: 3, scope: !5)
+!18 = !DILocation(line: 16, column: 3, scope: !5)
+!19 = !DILocation(line: 17, column: 3, scope: !5)