[TableGen] Add InstrInfoEmitter options for operand type/size mappings

- It seems operand type and operand size mappings are only used by
  a few backends. So disable their emission by default and have
  the backends that use these opt-in.

Author: jurahul

llvm/lib/Target/AVR/CMakeLists.txt

@@ -7,7 +7,7 @@ tablegen(LLVM AVRGenAsmWriter.inc -gen-asm-writer)
 tablegen(LLVM AVRGenCallingConv.inc -gen-callingconv)
 tablegen(LLVM AVRGenDAGISel.inc -gen-dag-isel)
 tablegen(LLVM AVRGenDisassemblerTables.inc -gen-disassembler)
-tablegen(LLVM AVRGenInstrInfo.inc -gen-instr-info)
+tablegen(LLVM AVRGenInstrInfo.inc -gen-instr-info -emit-operand-types)
 tablegen(LLVM AVRGenMCCodeEmitter.inc -gen-emitter)
 tablegen(LLVM AVRGenRegisterInfo.inc -gen-register-info)
 tablegen(LLVM AVRGenSubtargetInfo.inc -gen-subtarget)

llvm/lib/Target/M68k/CMakeLists.txt

@@ -5,7 +5,9 @@ set(LLVM_TARGET_DEFINITIONS M68k.td)
 tablegen(LLVM M68kGenGlobalISel.inc       -gen-global-isel)
 tablegen(LLVM M68kGenRegisterInfo.inc     -gen-register-info)
 tablegen(LLVM M68kGenRegisterBank.inc     -gen-register-bank)
-tablegen(LLVM M68kGenInstrInfo.inc        -gen-instr-info)
+tablegen(LLVM M68kGenInstrInfo.inc        -gen-instr-info
+                                          -emit-operand-types
+                                          -emit-logical-operand-size)
 tablegen(LLVM M68kGenSubtargetInfo.inc    -gen-subtarget)
 tablegen(LLVM M68kGenMCCodeEmitter.inc    -gen-emitter)
 tablegen(LLVM M68kGenMCPseudoLowering.inc -gen-pseudo-lowering)

llvm/lib/Target/X86/CMakeLists.txt

@@ -13,7 +13,8 @@ tablegen(LLVM X86GenExegesis.inc -gen-exegesis)
 tablegen(LLVM X86GenFastISel.inc -gen-fast-isel)
 tablegen(LLVM X86GenGlobalISel.inc -gen-global-isel)
 tablegen(LLVM X86GenInstrInfo.inc -gen-instr-info
-                                  -instr-info-expand-mi-operand-info=0)
+                                  -instr-info-expand-mi-operand-info=0
+                                  -emit-operand-types)
 tablegen(LLVM X86GenMnemonicTables.inc -gen-x86-mnemonic-tables -asmwriternum=1)
 tablegen(LLVM X86GenRegisterBank.inc -gen-register-bank)
 tablegen(LLVM X86GenRegisterInfo.inc -gen-register-info)

llvm/test/TableGen/get-operand-type-no-expand.td

@@ -30,7 +30,7 @@ def InstA : Instruction {
 }
 
 // RUN: llvm-tblgen -gen-instr-info -I %p/../../include %s \
-// RUN:   -instr-info-expand-mi-operand-info=1 \
+// RUN:   -emit-operand-types -instr-info-expand-mi-operand-info=1 \
 // RUN:   | FileCheck %s --check-prefix=CHECK-EXPAND
 // CHECK-EXPAND: #ifdef GET_INSTRINFO_OPERAND_TYPE
 // CHECK-EXPAND: OpcodeOperandTypes[] = {
@@ -39,7 +39,7 @@ def InstA : Instruction {
 // CHECK-EXPAND: #endif // GET_INSTRINFO_OPERAND_TYPE
 
 // RUN: llvm-tblgen -gen-instr-info -I %p/../../include %s \
-// RUN:   -instr-info-expand-mi-operand-info=0 \
+// RUN:   -emit-operand-types -instr-info-expand-mi-operand-info=0 \
 // RUN:   | FileCheck %s --check-prefix=CHECK-NOEXPAND
 // CHECK-NOEXPAND: #ifdef GET_INSTRINFO_OPERAND_TYPE
 // CHECK-NOEXPAND: OpcodeOperandTypes[] = {

llvm/test/TableGen/get-operand-type.td

@@ -1,4 +1,5 @@
-// RUN: llvm-tblgen -gen-instr-info -I %p/../../include %s | FileCheck %s
+// RUN: llvm-tblgen -gen-instr-info -emit-operand-types \
+// RUN:      -I %p/../../include %s | FileCheck %s
 
 // Check that getOperandType has the expected info in it
 

llvm/utils/TableGen/InstrInfoEmitter.cpp

@@ -41,6 +41,16 @@
 using namespace llvm;
 
 static cl::OptionCategory InstrInfoEmitterCat("Options for -gen-instr-info");
+
+static cl::opt<bool>
+    EnableOperandTypeMappings("emit-operand-types",
+                              cl::desc("Emit operand type mappings"),
+                              cl::cat(InstrInfoEmitterCat), cl::init(false));
+
+static cl::opt<bool> EnableLogicalOperandSizeMappings(
+    "emit-logical-operand-size", cl::desc("Emit logical operand size mappings"),
+    cl::cat(InstrInfoEmitterCat), cl::init(false));
+
 static cl::opt<bool> ExpandMIOperandInfo(
     "instr-info-expand-mi-operand-info",
     cl::desc("Expand operand's MIOperandInfo DAG into suboperands"),
@@ -338,8 +348,8 @@ void InstrInfoEmitter::emitOperandNameMappings(
 void InstrInfoEmitter::emitOperandTypeMappings(
     raw_ostream &OS, const CodeGenTarget &Target,
     ArrayRef<const CodeGenInstruction *> NumberedInstructions) {
-
   StringRef Namespace = Target.getInstNamespace();
+
   ArrayRef<const Record *> Operands =
       Records.getAllDerivedDefinitions("Operand");
   ArrayRef<const Record *> RegisterOperands =
@@ -461,10 +471,10 @@ void InstrInfoEmitter::emitOperandTypeMappings(
       SizeToOperandName[Size].push_back(Op->getName());
   }
   OS << "  default: return 0;\n";
-  for (const auto &KV : SizeToOperandName) {
-    for (const StringRef &OperandName : KV.second)
+  for (const auto &[Size, Names] : SizeToOperandName) {
+    for (const StringRef &OperandName : Names)
       OS << "  case OpTypes::" << OperandName << ":\n";
-    OS << "    return " << KV.first << ";\n\n";
+    OS << "    return " << Size << ";\n\n";
   }
   OS << "  }\n}\n";
   OS << "} // end namespace llvm::" << Namespace << "\n";
@@ -1124,11 +1134,15 @@ void InstrInfoEmitter::run(raw_ostream &OS) {
   Timer.startTimer("Emit operand name mappings");
   emitOperandNameMappings(OS, Target, NumberedInstructions);
 
-  Timer.startTimer("Emit operand type mappings");
-  emitOperandTypeMappings(OS, Target, NumberedInstructions);
+  if (EnableOperandTypeMappings) {
+    Timer.startTimer("Emit operand type mappings");
+    emitOperandTypeMappings(OS, Target, NumberedInstructions);
+  }
 
-  Timer.startTimer("Emit logical operand size mappings");
-  emitLogicalOperandSizeMappings(OS, TargetName, NumberedInstructions);
+  if (EnableLogicalOperandSizeMappings) {
+    Timer.startTimer("Emit logical operand size mappings");
+    emitLogicalOperandSizeMappings(OS, TargetName, NumberedInstructions);
+  }
 
   Timer.startTimer("Emit logical operand type mappings");
   emitLogicalOperandTypeMappings(OS, TargetName, NumberedInstructions);