Add extra check-line to test

NickGuy-Arm · NickGuy-Arm · commit a4f1d6ca2ab0 · 2025-07-17T12:39:37.000+01:00
diff --git a/llvm/test/Transforms/LoopVectorize/AArch64/maxbandwidth-regpressure.ll b/llvm/test/Transforms/LoopVectorize/AArch64/maxbandwidth-regpressure.ll
@@ -8,6 +8,7 @@ define i32 @dotp(ptr %a, ptr %b) #0 {
 ; CHECK-REGS-VP-NOT: LV(REG): Not considering vector loop of width vscale x 16 because it uses too many registers
 ; CHECK-REGS-VP: LV: Selecting VF: vscale x 8.
 ;
+; CHECK-NOREGS-VP: LV(REG): Not considering vector loop of width vscale x 8 because it uses too many registers
 ; CHECK-NOREGS-VP: LV(REG): Not considering vector loop of width vscale x 16 because it uses too many registers
 ; CHECK-NOREGS-VP: LV: Selecting VF: vscale x 4.
 entry:

Original file line number	Diff line number	Diff line change
`@@ -8,6 +8,7 @@ define i32 @dotp(ptr %a, ptr %b) #0 {`
`8`	`8`	`; CHECK-REGS-VP-NOT: LV(REG): Not considering vector loop of width vscale x 16 because it uses too many registers`
`9`	`9`	`; CHECK-REGS-VP: LV: Selecting VF: vscale x 8.`
`10`	`10`	`;`
	`11`	`+; CHECK-NOREGS-VP: LV(REG): Not considering vector loop of width vscale x 8 because it uses too many registers`
`11`	`12`	`; CHECK-NOREGS-VP: LV(REG): Not considering vector loop of width vscale x 16 because it uses too many registers`
`12`	`13`	`; CHECK-NOREGS-VP: LV: Selecting VF: vscale x 4.`
`13`	`14`	`entry:`