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[RISCV] Fix typo in comment. NFC
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llvm/lib/Target/RISCV/RISCVISelLowering.cpp

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@@ -16268,7 +16268,7 @@ static SDValue performXORCombine(SDNode *N, SelectionDAG &DAG,
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SDValue N1 = N->getOperand(1);
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// Pre-promote (i32 (xor (shl -1, X), ~0)) on RV64 with Zbs so we can use
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// (ADDI (BSET X0, X), -1). If we wait until/ type legalization, we'll create
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// (ADDI (BSET X0, X), -1). If we wait until type legalization, we'll create
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// RISCVISD:::SLLW and we can't recover it to use a BSET instruction.
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if (Subtarget.is64Bit() && Subtarget.hasStdExtZbs() &&
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N->getValueType(0) == MVT::i32 && isAllOnesConstant(N1) &&

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