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AMDGPU: Add encodings for minimum3/maximum3 f32 for gfx950 (#117600)
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‎llvm/lib/Target/AMDGPU/AMDGPU.td‎

Lines changed: 3 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -431,7 +431,9 @@ def FeatureGFX950Insts : SubtargetFeature<"gfx950-insts",
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FeatureBF8ConversionScaleInsts,
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FeatureFP4ConversionScaleInsts,
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FeatureFP6BF6ConversionScaleInsts,
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FeatureF16BF16ToFP6BF6ConversionScaleInsts]
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FeatureF16BF16ToFP6BF6ConversionScaleInsts,
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FeatureMinimum3Maximum3F32
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]
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>;
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def FeatureGFX10Insts : SubtargetFeature<"gfx10-insts",

‎llvm/lib/Target/AMDGPU/VOP3Instructions.td‎

Lines changed: 3 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -1937,6 +1937,9 @@ defm V_CVT_PK_BF16_F32: VOP3OpSel_Real_gfx9 <0x268>;
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defm V_CVT_SR_FP8_F32 : VOP3OpSel_Real_gfx9_forced_opsel2 <0x2a4>;
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defm V_CVT_SR_BF8_F32 : VOP3OpSel_Real_gfx9_forced_opsel2 <0x2a5>;
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defm V_MINIMUM3_F32 : VOP3_Real_vi <0x2a8>;
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defm V_MAXIMUM3_F32 : VOP3_Real_vi <0x2a9>;
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defm V_BITOP3_B16 : VOP3_Real_BITOP3_gfx9<0x233, "v_bitop3_b16">;
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defm V_BITOP3_B32 : VOP3_Real_BITOP3_gfx9<0x234, "v_bitop3_b32">;
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let OtherPredicates = [HasFP8ConversionScaleInsts] in {

‎llvm/test/MC/AMDGPU/gfx950_asm_features.s‎

Lines changed: 33 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -1149,3 +1149,36 @@ buffer_atomic_pk_add_bf16 v5, off, s[8:11], 0.5 offset:4095
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// NOT-GFX950: :[[@LINE+2]]:{{[0-9]+}}: error:
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// GFX950: buffer_atomic_pk_add_bf16 v5, off, s[8:11], -4.0 offset:4095 ; encoding: [0xff,0x0f,0x48,0xe1,0x00,0x05,0x02,0xf7]
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buffer_atomic_pk_add_bf16 v5, off, s[8:11], -4.0 offset:4095
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// NOT-GFX950: :[[@LINE+2]]:{{[0-9]+}}: error:
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// GFX950: v_maximum3_f32 v1, v2, v3, v4 ; encoding: [0x01,0x00,0xa9,0xd2,0x02,0x07,0x12,0x04]
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v_maximum3_f32 v1, v2, v3, v4
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// NOT-GFX950: :[[@LINE+2]]:{{[0-9]+}}: error:
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// GFX950: v_maximum3_f32 v1, -v2, -v3, -v4 ; encoding: [0x01,0x00,0xa9,0xd2,0x02,0x07,0x12,0xe4]
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v_maximum3_f32 v1, -v2, -v3, -v4
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// NOT-GFX950: :[[@LINE+2]]:{{[0-9]+}}: error:
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// GFX950: v_maximum3_f32 v1, -|v2|, -|v3|, -|v4| ; encoding: [0x01,0x07,0xa9,0xd2,0x02,0x07,0x12,0xe4]
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v_maximum3_f32 v1, -|v2|, -|v3|, -|v4|
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// NOT-GFX950: :[[@LINE+2]]:{{[0-9]+}}: error:
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// GFX950: v_maximum3_f32 v1, 0, 1.0, v3 ; encoding: [0x01,0x00,0xa9,0xd2,0x80,0xe4,0x0d,0x04]
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v_maximum3_f32 v1, 0.0, 1.0, v3
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// NOT-GFX950: :[[@LINE+2]]:{{[0-9]+}}: error:
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// GFX950: v_maximum3_f32 v2, 0, v3, 1.0 ; encoding: [0x02,0x00,0xa9,0xd2,0x80,0x06,0xca,0x03]
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v_maximum3_f32 v2, 0.0, v3, 1.0
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// NOT-GFX950: :[[@LINE+2]]:{{[0-9]+}}: error:
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// GFX950: v_maximum3_f32 v1, s8, v3, 1.0 ; encoding: [0x01,0x00,0xa9,0xd2,0x08,0x06,0xca,0x03]
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v_maximum3_f32 v1, s8, v3, 1.0
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// NOT-GFX950: :[[@LINE+2]]:{{[0-9]+}}: error:
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// GFX950: v_maximum3_f32 v1, v2, s8, v3 ; encoding: [0x01,0x00,0xa9,0xd2,0x02,0x11,0x0c,0x04]
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v_maximum3_f32 v1, v2, s8, v3
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// NOT-GFX950: :[[@LINE+2]]:{{[0-9]+}}: error:
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// GFX950: v_minimum3_f32 v0, v1, v2, v3 ; encoding: [0x00,0x00,0xa8,0xd2,0x01,0x05,0x0e,0x04]
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v_minimum3_f32 v0, v1, v2, v3

‎llvm/test/MC/AMDGPU/gfx950_err.s‎

Lines changed: 33 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -353,3 +353,36 @@ buffer_atomic_pk_add_bf16 v5, off, s[8:11], s3 offset:4095 dlc
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// GFX950: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction
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buffer_atomic_pk_add_bf16 v5, off, s[8:11], s3 offset:4095 glc slc dlc
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// GFX950: :[[@LINE+1]]:{{[0-9]+}}: error: instruction not supported on this GPU
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v_maximum3_f16 v0, v1, v2, v3
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// GFX950: :[[@LINE+1]]:{{[0-9]+}}: error: instruction not supported on this GPU
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v_minimum3_f16 v0, v1, v2, v3
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// GFX950: :[[@LINE+1]]:{{[0-9]+}}: error: instruction not supported on this GPU
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v_maximum_f16 v0, v1, v2
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// GFX950: :[[@LINE+1]]:{{[0-9]+}}: error: instruction not supported on this GPU
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v_minimum_f16 v0, v1, v2
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// GFX950: :[[@LINE+1]]:{{[0-9]+}}: error: instruction not supported on this GPU
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v_maximum_f32 v0, v1, v2
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// GFX950: :[[@LINE+1]]:{{[0-9]+}}: error: instruction not supported on this GPU
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v_minimum_f32 v0, v1, v2
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// GFX950: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand (violates constant bus restrictions)
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v_maximum3_f32 v0, s1, s2, v3
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// GFX950: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand (violates constant bus restrictions)
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v_maximum3_f32 v0, v3, s1, s2
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// GFX950: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand (violates constant bus restrictions)
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v_maximum3_f32 v0, s1, v3, s2
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// GFX950: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand (violates constant bus restrictions)
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v_minimum3_f32 v0, s1, s2, v3
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// GFX950: :[[@LINE+1]]:{{[0-9]+}}: error: literal operands are not supported
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v_minimum3_f32 v0, v1, v2, 0xdeadbeef

‎llvm/test/MC/Disassembler/AMDGPU/gfx950_dasm_vop3.txt‎

Lines changed: 24 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -857,3 +857,27 @@
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# GFX950: v_cvt_scalef32_2xpk16_bf6_f32 v[20:25], v[10:25], v[10:25], 11 ; encoding: [0x14,0x00,0x53,0xd2,0x0a,0x15,0x2e,0x02]
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0x14,0x00,0x53,0xd2,0x0a,0x15,0x2e,0x02
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# GFX950: v_maximum3_f32 v1, -v2, -v3, -v4 ; encoding: [0x01,0x00,0xa9,0xd2,0x02,0x07,0x12,0xe4]
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0x01,0x00,0xa9,0xd2,0x02,0x07,0x12,0xe4
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# GFX950: v_maximum3_f32 v1, -|v2|, -|v3|, -|v4| ; encoding: [0x01,0x07,0xa9,0xd2,0x02,0x07,0x12,0xe4]
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0x01,0x07,0xa9,0xd2,0x02,0x07,0x12,0xe4
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# GFX950: v_maximum3_f32 v1, 0, 1.0, v3 ; encoding: [0x01,0x00,0xa9,0xd2,0x80,0xe4,0x0d,0x04]
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0x01,0x00,0xa9,0xd2,0x80,0xe4,0x0d,0x04
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# GFX950: v_maximum3_f32 v1, s8, v3, 1.0 ; encoding: [0x01,0x00,0xa9,0xd2,0x08,0x06,0xca,0x03]
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0x01,0x00,0xa9,0xd2,0x08,0x06,0xca,0x03
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# GFX950: v_maximum3_f32 v1, v2, s8, v3 ; encoding: [0x01,0x00,0xa9,0xd2,0x02,0x11,0x0c,0x04]
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0x01,0x00,0xa9,0xd2,0x02,0x11,0x0c,0x04
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# GFX950: v_maximum3_f32 v1, v2, v3, v4 ; encoding: [0x01,0x00,0xa9,0xd2,0x02,0x07,0x12,0x04]
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0x01,0x00,0xa9,0xd2,0x02,0x07,0x12,0x04
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# GFX950: v_maximum3_f32 v2, 0, v3, 1.0 ; encoding: [0x02,0x00,0xa9,0xd2,0x80,0x06,0xca,0x03]
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0x02,0x00,0xa9,0xd2,0x80,0x06,0xca,0x03
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# GFX950: v_minimum3_f32 v0, v1, v2, v3 ; encoding: [0x00,0x00,0xa8,0xd2,0x01,0x05,0x0e,0x04]
883+
0x00,0x00,0xa8,0xd2,0x01,0x05,0x0e,0x04

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