Addressed the review comments1

JaydeepChauhan14 · JaydeepChauhan14 · commit a51c29dde730 · 2025-01-03T16:19:12.000+08:00
diff --git a/llvm/lib/Target/X86/X86ISelDAGToDAG.cpp b/llvm/lib/Target/X86/X86ISelDAGToDAG.cpp
@@ -5456,39 +5456,37 @@ void X86DAGToDAGISel::Select(SDNode *Node) {
     break;
   }
 
-  case X86ISD::FP_TO_SINT_SAT_CUSTOM:
-  case X86ISD::FP_TO_UINT_SAT_CUSTOM:
-    if (Subtarget->hasAVX10_2()) {
-      bool IsSigned = Node->getOpcode() == X86ISD::FP_TO_SINT_SAT_CUSTOM;
-      SDValue Op = Node->getOperand(0);
-      EVT VT = Node->getValueType(0);
-      EVT OpVT = Op.getValueType();
-      MachineSDNode *MachineNode;
-
-      if (VT == MVT::v4i32 && OpVT == MVT::v4f32) {
-        if (IsSigned)
-          MachineNode = CurDAG->getMachineNode(X86::VCVTTPD2DQSZ128rr, dl,
-                                               MVT::v4i32, Op);
-        else
-          MachineNode = CurDAG->getMachineNode(X86::VCVTTPD2UDQSZ128rr, dl,
-                                               MVT::v4i32, Op);
-      }
-
-      if ((VT == MVT::v2i64 && OpVT == MVT::v2f64)) {
-        if (IsSigned)
-          MachineNode = CurDAG->getMachineNode(X86::VCVTTPS2QQSZ128rr, dl,
-                                               MVT::v2i64, Op);
-        else
-          MachineNode = CurDAG->getMachineNode(X86::VCVTTPS2UQQSZ128rr, dl,
-                                               MVT::v2i64, Op);
-      }
+  case X86ISD::FP_TO_SINT_SAT:
+  case X86ISD::FP_TO_UINT_SAT: {
+    assert(Subtarget->hasAVX10_2() && "Unsupported node");
+    bool IsSigned = Node->getOpcode() == X86ISD::FP_TO_SINT_SAT;
+    SDValue Op = Node->getOperand(0);
+    EVT VT = Node->getValueType(0);
+    EVT OpVT = Op.getValueType();
+    MachineSDNode *MachineNode;
+
+    if (VT == MVT::v4i32 && OpVT == MVT::v4f32) {
+      if (IsSigned)
+        MachineNode =
+            CurDAG->getMachineNode(X86::VCVTTPD2DQSZ128rr, dl, MVT::v4i32, Op);
+      else
+        MachineNode =
+            CurDAG->getMachineNode(X86::VCVTTPD2UDQSZ128rr, dl, MVT::v4i32, Op);
+    }
 
-      SDValue NewNode = SDValue(MachineNode, 0);
-      ReplaceNode(Node, NewNode.getNode());
-      return;
+    if ((VT == MVT::v2i64 && OpVT == MVT::v2f64)) {
+      if (IsSigned)
+        MachineNode =
+            CurDAG->getMachineNode(X86::VCVTTPS2QQSZ128rr, dl, MVT::v2i64, Op);
+      else
+        MachineNode =
+            CurDAG->getMachineNode(X86::VCVTTPS2UQQSZ128rr, dl, MVT::v2i64, Op);
     }
-    break;
 
+    SDValue NewNode = SDValue(MachineNode, 0);
+    ReplaceNode(Node, NewNode.getNode());
+    return;
+  }
   case X86ISD::ANDNP:
     if (tryVPTERNLOG(Node))
       return;
diff --git a/llvm/lib/Target/X86/X86ISelLowering.cpp b/llvm/lib/Target/X86/X86ISelLowering.cpp
@@ -344,10 +344,14 @@ X86TargetLowering::X86TargetLowering(const X86TargetMachine &TM,
     setOperationAction(ISD::FP_TO_UINT_SAT, MVT::v2i32, Custom);
     setOperationAction(ISD::FP_TO_SINT_SAT, MVT::v2i32, Custom);
     for (MVT VT : {MVT::i32, MVT::v4i32, MVT::v8i32, MVT::v16i32, MVT::v2i64,
-                   MVT::v4i64, MVT::v8i64}) {
+                   MVT::v4i64}) {
       setOperationAction(ISD::FP_TO_UINT_SAT, VT, Legal);
       setOperationAction(ISD::FP_TO_SINT_SAT, VT, Legal);
     }
+    if (Subtarget.hasAVX10_2_512()) {
+      setOperationAction(ISD::FP_TO_UINT_SAT, MVT::v8i64, Legal);
+      setOperationAction(ISD::FP_TO_SINT_SAT, MVT::v8i64, Legal);
+    }
     if (Subtarget.is64Bit()) {
       setOperationAction(ISD::FP_TO_UINT_SAT, MVT::i64, Legal);
       setOperationAction(ISD::FP_TO_SINT_SAT, MVT::i64, Legal);
@@ -33686,11 +33690,9 @@ void X86TargetLowering::ReplaceNodeResults(SDNode *N,
     if (VT == MVT::v2i32 && OpVT == MVT::v2f64) {
       SDValue V4f32 = DAG.getNode(X86ISD::VFPROUND, dl, MVT::v4f32, Op);
       if (IsSigned)
-        V4I32 =
-            DAG.getNode(X86ISD::FP_TO_SINT_SAT_CUSTOM, dl, MVT::v4i32, V4f32);
+        V4I32 = DAG.getNode(X86ISD::FP_TO_SINT_SAT, dl, MVT::v4i32, V4f32);
       else
-        V4I32 =
-            DAG.getNode(X86ISD::FP_TO_UINT_SAT_CUSTOM, dl, MVT::v4i32, V4f32);
+        V4I32 = DAG.getNode(X86ISD::FP_TO_UINT_SAT, dl, MVT::v4i32, V4f32);
       Results.push_back(V4I32);
       return;
     }
@@ -34676,8 +34678,8 @@ const char *X86TargetLowering::getTargetNodeName(unsigned Opcode) const {
   NODE_NAME_CASE(VPERMV3)
   NODE_NAME_CASE(VPERMI)
   NODE_NAME_CASE(VPTERNLOG)
-  NODE_NAME_CASE(FP_TO_SINT_SAT_CUSTOM)
-  NODE_NAME_CASE(FP_TO_UINT_SAT_CUSTOM)
+  NODE_NAME_CASE(FP_TO_SINT_SAT)
+  NODE_NAME_CASE(FP_TO_UINT_SAT)
   NODE_NAME_CASE(VFIXUPIMM)
   NODE_NAME_CASE(VFIXUPIMM_SAE)
   NODE_NAME_CASE(VFIXUPIMMS)
@@ -56251,13 +56253,12 @@ static SDValue combineFP_TO_xINT_SAT(SDNode *N, SelectionDAG &DAG,
     SDValue V2F64 =
         DAG.getNode(ISD::FP_EXTEND, dl, MVT::v2f64, N->getOperand(0));
 
-    // Select the FP_TO_SINT_SAT_CUSTOM/FP_TO_UINT_SAT_CUSTOM node
+    // Select the FP_TO_SINT_SAT/FP_TO_UINT_SAT node
     if (IsSigned)
-      return DAG.getNode(X86ISD::FP_TO_SINT_SAT_CUSTOM, dl, MVT::v2i64, V2F64);
-    else
-      return DAG.getNode(X86ISD::FP_TO_UINT_SAT_CUSTOM, dl, MVT::v2i64, V2F64);
-  }
+      return DAG.getNode(X86ISD::FP_TO_SINT_SAT, dl, MVT::v2i64, V2F64);
 
+    return DAG.getNode(X86ISD::FP_TO_UINT_SAT, dl, MVT::v2i64, V2F64);
+  }
   return SDValue();
 }
 
diff --git a/llvm/lib/Target/X86/X86ISelLowering.h b/llvm/lib/Target/X86/X86ISelLowering.h
@@ -909,8 +909,8 @@ namespace llvm {
     FLDENVm,
 
     // Custom handling for FP_TO_xINT_SAT
-    FP_TO_SINT_SAT_CUSTOM,
-    FP_TO_UINT_SAT_CUSTOM,
+    FP_TO_SINT_SAT,
+    FP_TO_UINT_SAT,
 
     /// This instruction implements FP_TO_SINT with the
     /// integer destination in memory and a FP reg source.  This corresponds
diff --git a/llvm/test/CodeGen/X86/avx10_2_512fptosi_satcvtds.ll b/llvm/test/CodeGen/X86/avx10_2_512fptosi_satcvtds.ll
@@ -1,122 +1,85 @@
 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
-; RUN: llc < %s -mtriple=i686-linux -mattr=+avx10.2-512 | FileCheck %s --check-prefix=X86
-; RUN: llc < %s -mtriple=x86_64-linux -mattr=+avx10.2-512 | FileCheck %s --check-prefix=X64
+; RUN: llc < %s -mtriple=i686-linux -mattr=+avx10.2-512 | FileCheck %s --check-prefixes=CHECK,X86
+; RUN: llc < %s -mtriple=x86_64-linux -mattr=+avx10.2-512 | FileCheck %s --check-prefixes=CHECK,X64
 
 ; VCVTTPD2DQS
 define <8 x i32> @test_signed_v8i32_v8f64(<8 x double> %f) nounwind {
-; X86-LABEL: test_signed_v8i32_v8f64:
-; X86:       # %bb.0:
-; X86-NEXT:    vcvttpd2dqs %zmm0, %ymm0
-; X86-NEXT:    retl
-;
-; X64-LABEL: test_signed_v8i32_v8f64:
-; X64:       # %bb.0:
-; X64-NEXT:    vcvttpd2dqs %zmm0, %ymm0
-; X64-NEXT:    retq
+; CHECK-LABEL: test_signed_v8i32_v8f64:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vcvttpd2dqs %zmm0, %ymm0
+; CHECK-NEXT:    ret{{[l|q]}}
   %x = call  <8 x i32> @llvm.fptosi.sat.v8i32.v8f64(<8 x double> %f)
   ret <8 x i32> %x
 }
 
 ; VCVTTPD2QQS
 define <8 x i64> @test_signed_v8i64_v8f64(<8 x double> %f) nounwind {
-; X86-LABEL: test_signed_v8i64_v8f64:
-; X86:       # %bb.0:
-; X86-NEXT:    vcvttpd2qqs %zmm0, %zmm0
-; X86-NEXT:    retl
-;
-; X64-LABEL: test_signed_v8i64_v8f64:
-; X64:       # %bb.0:
-; X64-NEXT:    vcvttpd2qqs %zmm0, %zmm0
-; X64-NEXT:    retq
+; CHECK-LABEL: test_signed_v8i64_v8f64:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vcvttpd2qqs %zmm0, %zmm0
+; CHECK-NEXT:    ret{{[l|q]}}
   %x = call <8 x i64> @llvm.fptosi.sat.v8i64.v8f64(<8 x double> %f)
   ret <8 x i64> %x
 }
 
 ; VCVTTPD2UDQS
 define <8 x i32> @test_unsigned_v8i32_v8f64(<8 x double> %f) nounwind {
-; X86-LABEL: test_unsigned_v8i32_v8f64:
-; X86:       # %bb.0:
-; X86-NEXT:    vcvttpd2udqs %zmm0, %ymm0
-; X86-NEXT:    retl
-;
-; X64-LABEL: test_unsigned_v8i32_v8f64:
-; X64:       # %bb.0:
-; X64-NEXT:    vcvttpd2udqs %zmm0, %ymm0
-; X64-NEXT:    retq
+; CHECK-LABEL: test_unsigned_v8i32_v8f64:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vcvttpd2udqs %zmm0, %ymm0
+; CHECK-NEXT:    ret{{[l|q]}}
   %x = call  <8 x i32> @llvm.fptoui.sat.v8i32.v8f64(<8 x double> %f)
  ret <8 x i32> %x
 }
 
 ; VCVTTPD2UQQS
 define <8 x i64> @test_unsigned_v8i64_v8f64(<8 x double> %f) nounwind {
-; X86-LABEL: test_unsigned_v8i64_v8f64:
-; X86:       # %bb.0:
-; X86-NEXT:    vcvttpd2uqqs %zmm0, %zmm0
-; X86-NEXT:    retl
-;
-; X64-LABEL: test_unsigned_v8i64_v8f64:
-; X64:       # %bb.0:
-; X64-NEXT:    vcvttpd2uqqs %zmm0, %zmm0
-; X64-NEXT:    retq
+; CHECK-LABEL: test_unsigned_v8i64_v8f64:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vcvttpd2uqqs %zmm0, %zmm0
+; CHECK-NEXT:    ret{{[l|q]}}
   %x = call  <8 x i64> @llvm.fptoui.sat.v8i64.v8f64(<8 x double> %f)
   ret <8 x i64> %x
 }
 
 ; VCVTTPS2DQS
 define <16 x i32> @test_signed_v16i32_v16f32(<16 x float> %f) nounwind {
-; X86-LABEL: test_signed_v16i32_v16f32:
-; X86:       # %bb.0:
-; X86-NEXT:    vcvttps2dqs %zmm0, %zmm0
-; X86-NEXT:    retl
-;
-; X64-LABEL: test_signed_v16i32_v16f32:
-; X64:       # %bb.0:
-; X64-NEXT:    vcvttps2dqs %zmm0, %zmm0
-; X64-NEXT:    retq
+; CHECK-LABEL: test_signed_v16i32_v16f32:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vcvttps2dqs %zmm0, %zmm0
+; CHECK-NEXT:    ret{{[l|q]}}
   %x = call  <16 x i32> @llvm.fptosi.sat.v16i32.v16f32(<16 x float> %f)
   ret <16 x i32> %x
 }
 
 ; VCVTTPS2UDQS
 define <16 x i32> @test_unsigned_v16i32_v16f32(<16 x float> %f) nounwind {
-; X86-LABEL: test_unsigned_v16i32_v16f32:
-; X86:       # %bb.0:
-; X86-NEXT:    vcvttps2udqs %zmm0, %zmm0
-; X86-NEXT:    retl
-;
-; X64-LABEL: test_unsigned_v16i32_v16f32:
-; X64:       # %bb.0:
-; X64-NEXT:    vcvttps2udqs %zmm0, %zmm0
-; X64-NEXT:    retq
+; CHECK-LABEL: test_unsigned_v16i32_v16f32:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vcvttps2udqs %zmm0, %zmm0
+; CHECK-NEXT:    ret{{[l|q]}}
   %x = call  <16 x i32> @llvm.fptoui.sat.v16i32.v16f32(<16 x float> %f)
   ret <16 x i32> %x
 }
 ; VCVTTPS2QQS
 define <8 x i64> @test_signed_v8i64_v8f32(<8 x float> %f) nounwind {
-; X86-LABEL: test_signed_v8i64_v8f32:
-; X86:       # %bb.0:
-; X86-NEXT:    vcvttps2qqs %ymm0, %zmm0
-; X86-NEXT:    retl
-;
-; X64-LABEL: test_signed_v8i64_v8f32:
-; X64:       # %bb.0:
-; X64-NEXT:    vcvttps2qqs %ymm0, %zmm0
-; X64-NEXT:    retq
+; CHECK-LABEL: test_signed_v8i64_v8f32:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vcvttps2qqs %ymm0, %zmm0
+; CHECK-NEXT:    ret{{[l|q]}}
   %x = call  <8 x i64> @llvm.fptosi.sat.v8i64.v8f32(<8 x float> %f)
   ret <8 x i64> %x
 }
 
 ; VCVTTPS2UQQS
 define <8 x i64> @test_unsigned_v8i64_v8f32(<8 x float> %f) nounwind {
-; X86-LABEL: test_unsigned_v8i64_v8f32:
-; X86:       # %bb.0:
-; X86-NEXT:    vcvttps2uqqs %ymm0, %zmm0
-; X86-NEXT:    retl
-;
-; X64-LABEL: test_unsigned_v8i64_v8f32:
-; X64:       # %bb.0:
-; X64-NEXT:    vcvttps2uqqs %ymm0, %zmm0
-; X64-NEXT:    retq
+; CHECK-LABEL: test_unsigned_v8i64_v8f32:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vcvttps2uqqs %ymm0, %zmm0
+; CHECK-NEXT:    ret{{[l|q]}}
   %x = call  <8 x i64> @llvm.fptoui.sat.v8i64.v8f32(<8 x float> %f)
   ret <8 x i64> %x
 }
+;; NOTE: These prefixes are unused and the list is autogenerated. Do not add tests below this line:
+; X64: {{.*}}
+; X86: {{.*}}
diff --git a/llvm/test/CodeGen/X86/avx10_2fptosi_satcvtds.ll b/llvm/test/CodeGen/X86/avx10_2fptosi_satcvtds.ll
