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Revert "[DAG] Fold (umin (sub a b) a) -> (usubo a b); (select usubo.1 a usubo.0)" (#167854)
Reverts #161651 due to downstream bad codegen reports
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llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp

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Original file line numberDiff line numberDiff line change
@@ -6219,25 +6219,6 @@ SDValue DAGCombiner::visitIMINMAX(SDNode *N) {
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SDLoc(N), VT, N0, N1))
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return SD;
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if (TLI.isOperationLegalOrCustom(ISD::USUBO, VT) &&
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!TLI.isOperationLegalOrCustom(ISD::UMIN, VT)) {
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SDValue B;
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// (umin (sub a, b), a) -> (usubo a, b); (select usubo.1, a, usubo.0)
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if (sd_match(N0, m_Sub(m_Specific(N1), m_Value(B)))) {
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SDVTList VTs = DAG.getVTList(VT, getSetCCResultType(VT));
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SDValue USO = DAG.getNode(ISD::USUBO, DL, VTs, N1, B);
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return DAG.getSelect(DL, VT, USO.getValue(1), N1, USO.getValue(0));
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}
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// (umin a, (sub a, b)) -> (usubo a, b); (select usubo.1, a, usubo.0)
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if (sd_match(N1, m_Sub(m_Specific(N0), m_Value(B)))) {
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SDVTList VTs = DAG.getVTList(VT, getSetCCResultType(VT));
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SDValue USO = DAG.getNode(ISD::USUBO, DL, VTs, N0, B);
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return DAG.getSelect(DL, VT, USO.getValue(1), N0, USO.getValue(0));
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}
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}
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// Simplify the operands using demanded-bits information.
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if (SimplifyDemandedBits(SDValue(N, 0)))
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return SDValue(N, 0);

llvm/test/CodeGen/AArch64/umin-sub-to-usubo-select-combine.ll

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llvm/test/CodeGen/X86/umin-sub-to-usubo-select-combine.ll

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